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DS2156
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul applications. The backplane is userconfigurable for a TDM or UTOPIA II bus interface. The DS2156 is composed of a line interface unit (LIU), framer, HDLC controllers, and a UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155. The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75 coax and 120 twisted cables. The receive interface provides network termination and recovers clock and data from the network.
FEATURES

Complete T1/DS1/ISDN-PRI/J1 Transceiver Functionality Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality User-Selectable TDM or UTOPIA II Bus Interface Long-Haul and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping CMI Coder/Decoder for Optical I/F Crystal-Less Jitter Attenuator Fully Independent Transmit and Receive Functionality Dual HDLC Controllers Programmable BERT Generator and Detector Internal Software-Selectable Receive and Transmit-Side Termination Resistors for 75/100/120 T1 and E1 Interfaces Dual Two-Frame Elastic-Store Slip Buffers that Connect to Asynchronous Backplanes Up to 16.384MHz 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Network Clock
APPLICATIONS
Inverse Mux ATM (IMA) T1/E1/J1 Line Cards Switches and Routers Add-Drop Multiplexers
Features continued on page 8.
ORDERING INFORMATION
PART DS2156L DS2156LN TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 100 LQFP 100 LQFP
UTOPIA T1/E1/J1 NETWORK
DS2156 T1/E1/J1 TDM/UTOPIA
BACKPLANE
TDM
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here:www.maxim-ic.com/errata.
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110502
DS2156
TABLE OF CONTENTS
1. 2. MAIN FEATURES........................................................................................................................................8 DETAILED DESCRIPTION......................................................................................................................11 2.1 BLOCK DIAGRAM...........................................................................................................................................13 FIGURE 2-1. BLOCK DIAGRAM................................................................................................................................13 FIGURE 2-2. RECEIVE AND TRANSMIT LIU (TDM BACKPLANE ENABLED)...........................................................14 FIGURE 2-3. RECEIVE AND TRANSMIT LIU (UTOPIA BACKPLANE ENABLED).....................................................15 FIGURE 2-4. RECEIVE AND TRANSMIT FRAMER/HDLC..........................................................................................16 FIGURE 2-5. BACKPLANE INTERFACE (TDM BACKPLANE ENABLED) ...................................................................17 FIGURE 2-6. BACKPLANE INTERFACE (UTOPIA BUS ENABLED)...........................................................................18 3. PIN FUNCTION DESCRIPTION .............................................................................................................19 3.1 TDM BACKPLANE .........................................................................................................................................19 3.1.1 Transmit Side ........................................................................................................................................19 3.1.2 Receive Side ..........................................................................................................................................22 3.2 UTOPIA BUS.................................................................................................................................................25 3.2.1 Receive Side ..........................................................................................................................................25 3.2.2 Transmit Side ........................................................................................................................................26 3.3 PARALLEL CONTROL PORT PINS ...................................................................................................................27 3.4 EXTENDED SYSTEM INFORMATION BUS........................................................................................................28 3.5 USER OUTPUT PORT PINS ..............................................................................................................................29 3.6 JTAG TEST ACCESS PORT PINS.....................................................................................................................30 3.7 LINE INTERFACE PINS ....................................................................................................................................31 3.8 SUPPLY PINS ..................................................................................................................................................32 3.9 L AND G PACKAGE PINOUT...........................................................................................................................33 TABLE 3-A. PIN DESCRIPTION SORTED BY PIN NUMBER (TDM BACKPLANE ENABLED) .....................................33 TABLE 3-B. PIN DESCRIPTION SORTED BY PIN NUMBER (UTOPIA BACKPLANE ENABLED) ................................35 3.10 10MM CSBGA PIN CONFIGURATION ........................................................................................................37 FIGURE 3-1. 10MM CSBGA PIN CONFIGURATION (TDM SIGNALS SHOWN) .........................................................37 4. PARALLEL PORT .....................................................................................................................................38 4.1 REGISTER MAP ..............................................................................................................................................38 TABLE 4-A. REGISTER MAP SORTED BY ADDRESS ................................................................................................38 4.2 UTOPIA BUS REGISTERS ..............................................................................................................................44 TABLE 4-B. UTOPIA REGISTER MAP.....................................................................................................................44 5. 6. SPECIAL PER-CHANNEL REGISTER OPERATION.........................................................................45 PROGRAMMING MODEL.......................................................................................................................47 FIGURE 6-1. PROGRAMMING SEQUENCE.................................................................................................................47 6.1 POWER-UP SEQUENCE...................................................................................................................................48 6.1.1 Master Mode Register...........................................................................................................................48 6.2 INTERRUPT HANDLING ..................................................................................................................................49 6.3 STATUS REGISTERS........................................................................................................................................49 6.4 INFORMATION REGISTERS .............................................................................................................................50 6.5 INTERRUPT INFORMATION REGISTERS ..........................................................................................................50 7. 8. 8.1 CLOCK MAP ..............................................................................................................................................51 FIGURE 7-1. CLOCK MAP (TDM MODE).................................................................................................................51 T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................52 T1 CONTROL REGISTERS ...............................................................................................................................52 2 of 262
DS2156 8.2 T1 TRANSMIT TRANSPARENCY .....................................................................................................................57 8.3 AIS-CI AND RAI-CI GENERATION AND DETECTION ....................................................................................57 8.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.......................................................................58 TABLE 8-A. T1 ALARM CRITERIA ..........................................................................................................................60 9. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS..............................................61 9.1 E1 CONTROL REGISTERS ...............................................................................................................................61 TABLE 9-A. E1 SYNC/RESYNC CRITERIA ...............................................................................................................62 9.2 AUTOMATIC ALARM GENERATION................................................................................................................65 9.3 E1 INFORMATION REGISTERS........................................................................................................................66 TABLE 9-B. E1 ALARM CRITERIA...........................................................................................................................67 10. 10.1 11. 12. 12.1 13. COMMON CONTROL AND STATUS REGISTERS ............................................................................68 T1/E1 STATUS REGISTERS ........................................................................................................................69 I/O PIN CONFIGURATION OPTIONS...................................................................................................75 LOOPBACK CONFIGURATION ............................................................................................................77 PER-CHANNEL LOOPBACK ........................................................................................................................79 ERROR COUNT REGISTERS .................................................................................................................81
13.1 LINE-CODE VIOLATION COUNT REGISTER (LCVCR)...............................................................................82 13.1.1 T1 Operation.........................................................................................................................................82 TABLE 13-A. T1 LINE-CODE VIOLATION COUNTING OPTIONS..............................................................................82 13.1.2 E1 Operation.........................................................................................................................................82 TABLE 13-B. E1 LINE-CODE VIOLATION COUNTING OPTIONS ..............................................................................82 13.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) ..............................................................................84 13.2.1 T1 Operation.........................................................................................................................................84 TABLE 13-C. T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS ................................................................84 13.2.2 E1 Operation.........................................................................................................................................84 13.3 FRAMES OUT-OF-SYNC COUNT REGISTER (FOSCR)................................................................................85 13.3.1 T1 Operation.........................................................................................................................................85 TABLE 13-D. T1 FRAMES OUT-OF-SYNC COUNTING ARRANGEMENTS .................................................................85 13.3.2 E1 Operation.........................................................................................................................................85 13.4 E-BIT COUNTER (EBCR)...........................................................................................................................86 14. 15. DS0 MONITORING FUNCTION .............................................................................................................87 SIGNALING OPERATION .......................................................................................................................89
15.1 RECEIVE SIGNALING .................................................................................................................................89 FIGURE 15-1. SIMPLIFIED DIAGRAM OF RECEIVE SIGNALING PATH ......................................................................89 15.1.1 Processor-Based Signaling...................................................................................................................89 15.1.2 Hardware-Based Receive Signaling .....................................................................................................90 15.2 TRANSMIT SIGNALING...............................................................................................................................95 FIGURE 15-2. SIMPLIFIED DIAGRAM OF TRANSMIT SIGNALING PATH ...................................................................95 15.2.1 Processor-Based Mode .........................................................................................................................95 TABLE 15-A. TIME SLOT NUMBERING SCHEMES ...................................................................................................96 15.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode............................................................99 15.2.3 Software Signaling Insertion-Enable Registers, T1 Mode..................................................................101 15.2.4 Hardware-Based Mode.......................................................................................................................101 16. PER-CHANNEL IDLE CODE GENERATION ....................................................................................102 TABLE 16-A. IDLE-CODE ARRAY ADDRESS MAPPING .........................................................................................102 16.1 IDLE-CODE PROGRAMMING EXAMPLES..................................................................................................103 TABLE 16-B. GRIC AND GTIC FUNCTIONS .........................................................................................................104 3 of 262
DS2156 17. 18. CHANNEL BLOCKING REGISTERS ..................................................................................................107 ELASTIC STORES OPERATION..........................................................................................................110
18.1 RECEIVE SIDE ..........................................................................................................................................113 18.1.1 T1 Mode ..............................................................................................................................................113 18.1.2 E1 Mode..............................................................................................................................................113 18.2 TRANSMIT SIDE .......................................................................................................................................113 18.2.1 T1 Mode ..............................................................................................................................................114 18.2.2 E1 Mode..............................................................................................................................................114 18.3 ELASTIC STORES INITIALIZATION ...........................................................................................................114 TABLE 18-A. ELASTIC STORE DELAY AFTER INITIALIZATION.............................................................................114 18.4 MINIMUM DELAY MODE .........................................................................................................................114 19. 20. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).....................................................115 T1 BIT-ORIENTED CODE (BOC) CONTROLLER............................................................................116 FIGURE 19-1. CRC-4 RECALCULATE METHOD ....................................................................................................115 20.1 TRANSMIT BOC.......................................................................................................................................116 Transmit a BOC ................................................................................................................................................116 20.2 RECEIVE BOC .........................................................................................................................................116 Receive a BOC ..................................................................................................................................................116 21. 21.1 21.2 21.3 22. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) ........................119 METHOD 1: HARDWARE SCHEME ...........................................................................................................119 METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ................................................119 METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME..........................................122 HDLC CONTROLLERS ..........................................................................................................................132
22.1 BASIC OPERATION DETAILS....................................................................................................................132 22.2 HDLC CONFIGURATION..........................................................................................................................132 TABLE 22-A. HDLC CONTROLLER REGISTERS ....................................................................................................133 22.2.1 FIFO Control......................................................................................................................................136 22.3 HDLC MAPPING......................................................................................................................................137 22.3.1 Receive................................................................................................................................................137 22.3.2 Transmit ..............................................................................................................................................139 22.3.3 FIFO Information ...............................................................................................................................144 22.3.4 Receive Packet-Bytes Available..........................................................................................................144 22.3.5 HDLC FIFOs ......................................................................................................................................145 22.4 RECEIVE HDLC CODE EXAMPLE............................................................................................................146 22.5 LEGACY FDL SUPPORT (T1 MODE)........................................................................................................146 22.5.1 Overview .............................................................................................................................................146 22.5.2 Receive Section ...................................................................................................................................146 22.5.3 Transmit Section .................................................................................................................................148 22.6 D4/SLC-96 OPERATION ..........................................................................................................................148 23. LINE INTERFACE UNIT (LIU) .............................................................................................................149 23.1 LIU OPERATION ......................................................................................................................................149 23.2 RECEIVER ................................................................................................................................................149 23.2.1 Receive Level Indicator and Threshold Interrupt ...............................................................................150 23.2.2 Receive G.703 Synchronization Signal (E1 Mode).............................................................................150 23.2.3 Monitor Mode .....................................................................................................................................150 FIGURE 23-1. TYPICAL MONITOR APPLICATION...................................................................................................150 23.3 TRANSMITTER .........................................................................................................................................151 23.3.1 Transmit Short-Circuit Detector/Limiter............................................................................................151 4 of 262
DS2156 23.3.2 Transmit Open-Circuit Detector.........................................................................................................151 23.3.3 Transmit BPV Error Insertion ............................................................................................................151 23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................................151 23.4 MCLK PRESCALER .................................................................................................................................152 23.5 JITTER ATTENUATOR...............................................................................................................................152 23.6 CMI (CODE MARK INVERSION) OPTION.................................................................................................152 FIGURE 23-2. CMI CODING ..................................................................................................................................152 23.7 LIU CONTROL REGISTERS ......................................................................................................................153 23.8 RECOMMENDED CIRCUITS.......................................................................................................................160 FIGURE 23-3. BASIC INTERFACE ...........................................................................................................................160 FIGURE 23-4. PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION ..............................................161 23.9 COMPONENT SPECIFICATIONS.................................................................................................................162 TABLE 23-A. TRANSFORMER SPECIFICATIONS .....................................................................................................162 FIGURE 23-5. E1 TRANSMIT PULSE TEMPLATE ....................................................................................................163 FIGURE 23-6. T1 TRANSMIT PULSE TEMPLATE ....................................................................................................163 FIGURE 23-7. JITTER TOLERANCE.........................................................................................................................164 FIGURE 23-8. JITTER TOLERANCE (E1 MODE)......................................................................................................164 FIGURE 23-9. JITTER ATTENUATION (T1 MODE)..................................................................................................165 FIGURE 23-10. JITTER ATTENUATION (E1 MODE)................................................................................................165 FIGURE 23-11. OPTIONAL CRYSTAL CONNECTIONS .............................................................................................166 24. UTOPIA BACKPLANE INTERFACE ...................................................................................................167 24.1 DESCRIPTION ...........................................................................................................................................167 24.1.1 List of Applicable Standards...............................................................................................................167 24.1.2 Acronyms and Definitions...................................................................................................................167 24.2 UTOPIA CLOCK MODES.........................................................................................................................168 FIGURE 24-1. UTOPIA CLOCKING CONFIGURATIONS .........................................................................................168 24.3 FULL T1/E1 MODE AND CLEAR-CHANNEL E1 MODE ............................................................................168 24.4 FRACTIONAL T1/E1 MODE ......................................................................................................................169 TABLE 24-A. UTOPIA CLOCK MODE CONFIGURATION ......................................................................................169 24.5 TRANSMIT OPERATION............................................................................................................................170 24.5.1 UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV ......................................................170 FIGURE 24-2. POLLING PHASE AND SELECTION PHASE AT TRANSMIT INTERFACE..............................................171 FIGURE 24-3. END AND RESTART OF CELL AT TRANSMIT INTERFACE................................................................172 FIGURE 24-4. TRANSMISSION TO PHY PAUSED FOR THREE CYCLES...................................................................173 24.5.2 UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV) .................................................173 FIGURE 24-5. EXAMPLE OF DIRECT STATUS INDICATION, TRANSMIT DIRECTION ..............................................174 24.5.3 Transmit Processing ...........................................................................................................................175 FIGURE 24-6. TRANSMIT CELL FLOW ...................................................................................................................175 24.6 RECEIVE OPERATION...............................................................................................................................176 24.6.1 Receive Processing .............................................................................................................................176 FIGURE 24-7. CELL-DELINEATION STATE DIAGRAM ...........................................................................................176 FIGURE 24-8. HEADER CORRECTION STATE MACHINE ........................................................................................177 24.6.2 UTOPIA Side Receive: Muxed Mode with One Receive CLAV ..........................................................178 FIGURE 24-9. POLLING PHASE AND SELECTION AT RECEIVE INTERFACE ............................................................178 FIGURE 24-10. END AND RESTART OF CELL TRANSMISSION AT RECEIVE INTERFACE ........................................179 24.6.3 UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV) .....................................................179 FIGURE 24-11. EXAMPLE OF DIRECT STATUS INDICATION, RECEIVE DIRECTION ...............................................180 24.7 REGISTER DEFINITIONS ...........................................................................................................................181 24.8 RECEIVE FIFO OVERRUN........................................................................................................................192 24.9 UTOPIA DIAGNOSTIC LOOPBACK..........................................................................................................192 25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION........................193 5 of 262
DS2156 26. BERT FUNCTION....................................................................................................................................200
26.1 STATUS ....................................................................................................................................................200 26.2 MAPPING .................................................................................................................................................200 FIGURE 26-1. SIMPLIFIED DIAGRAM OF BERT IN NETWORK DIRECTION ............................................................201 FIGURE 26-2. SIMPLIFIED DIAGRAM OF BERT IN BACKPLANE DIRECTION.........................................................201 26.3 BERT REGISTER DESCRIPTIONS .............................................................................................................202 26.4 BERT REPETITIVE PATTERN SET............................................................................................................206 26.5 BERT BIT COUNTER ...............................................................................................................................207 26.6 BERT ERROR COUNTER .........................................................................................................................208 27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)..................................................210 TABLE 27-A. TRANSMIT ERROR-INSERTION SETUP SEQUENCE ...........................................................................210 27.1 NUMBER-OF-ERRORS REGISTERS............................................................................................................212 TABLE 27-B. ERROR INSERTION EXAMPLES.........................................................................................................212 27.1.1 Number-of-Errors Left Register..........................................................................................................213 28. INTERLEAVED PCM BUS OPERATION (IBO).................................................................................214 28.1 CHANNEL INTERLEAVE ...........................................................................................................................214 28.2 FRAME INTERLEAVE................................................................................................................................214 FIGURE 28-1. IBO EXAMPLE ................................................................................................................................216 29. 30. 31. 31.1 31.2 32. 33. EXTENDED SYSTEM INFORMATION BUS (ESIB) .........................................................................217 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ..........................................................221 FRACTIONAL T1/E1 SUPPORT ...........................................................................................................221 TDM BACKPLANE MODE........................................................................................................................221 UTOPIA BACKPLANE MODE ..................................................................................................................222 USER-PROGRAMMABLE OUTPUT PINS..........................................................................................223 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................224 FIGURE 29-1. ESIB GROUP OF FOUR DS2156S ....................................................................................................217
33.1 DESCRIPTION ...........................................................................................................................................224 FIGURE 33-1. JTAG FUNCTIONAL BLOCK DIAGRAM ...........................................................................................224 FIGURE 33-2. TAP CONTROLLER STATE DIAGRAM .............................................................................................227 33.2 INSTRUCTION REGISTER..........................................................................................................................227 TABLE 33-A. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE................................................................228 SAMPLE/PRELOAD .........................................................................................................................................228 BYPASS .............................................................................................................................................................228 EXTEST .............................................................................................................................................................228 CLAMP..............................................................................................................................................................228 HIGHZ...............................................................................................................................................................228 IDCODE............................................................................................................................................................228 TABLE 33-B. ID CODE STRUCTURE ......................................................................................................................229 TABLE 33-C. DEVICE ID CODES ...........................................................................................................................229 33.3 TEST REGISTERS......................................................................................................................................229 33.4 BOUNDARY SCAN REGISTER ...................................................................................................................229 33.5 BYPASS REGISTER ...................................................................................................................................229 33.6 IDENTIFICATION REGISTER .....................................................................................................................229 TABLE 33-D. BOUNDARY SCAN CONTROL BITS...................................................................................................230 34. 34.1 FUNCTIONAL TIMING DIAGRAMS...................................................................................................233 T1 MODE .................................................................................................................................................233 6 of 262
DS2156 FIGURE 34-1. RECEIVE-SIDE D4 TIMING ..............................................................................................................233 FIGURE 34-2. RECEIVE-SIDE ESF TIMING ............................................................................................................233 FIGURE 34-3. RECEIVE-SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) ..........................................234 FIGURE 34-4. RECEIVE-SIDE 1.544MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED).......................234 FIGURE 34-5. RECEIVE-SIDE 2.048MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED).......................235 FIGURE 34-6. TRANSMIT SIDE D4 TIMING............................................................................................................235 FIGURE 34-7. TRANSMIT-SIDE ESF TIMING..........................................................................................................236 FIGURE 34-8. TRANSMIT-SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED) .....................................236 FIGURE 34-9. TRANSMIT-SIDE 1.544MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) ....................237 FIGURE 34-10. TRANSMIT-SIDE 2.048MHZ BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) ..................237 34.2 E1 MODE .................................................................................................................................................238 FIGURE 34-11. RECEIVE-SIDE TIMING............................................................................................................238 FIGURE 34-12. RECEIVE-SIDE BOUNDARY TIMING (WITH ELASTIC STORE DISABLED)........................................238 FIGURE 34-13. RECEIVE-SIDE BOUNDARY TIMING, RSYSCLK = 1.544MHZ (ELASTIC STORE ENABLED) .......239 FIGURE 34-14. RECEIVE-SIDE BOUNDARY TIMING, RSYSCLK = 2.048MHZ (ELASTIC STORE ENABLED) .......239 FIGURE 34-15. RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING..................................................................240 FIGURE 34-16. RECEIVE IBO FRAME INTERLEAVE MODE TIMING ......................................................................241 FIGURE 34-17. G.802 TIMING, E1 MODE ONLY ...................................................................................................242 FIGURE 34-18. TRANSMIT-SIDE TIMING ...............................................................................................................242 FIGURE 34-19. TRANSMIT-SIDE BOUNDARY TIMING (ELASTIC STORE DISABLED) .............................................243 FIGURE 34-20. TRANSMIT-SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHZ (ELASTIC STORE ENABLED) ....243 FIGURE 34-22. TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING...............................................................245 FIGURE 34-23. TRANSMIT IBO FRAME INTERLEAVE MODE TIMING ...................................................................246 35. 36. OPERATING PARAMETERS ................................................................................................................247 AC TIMING PARAMETERS AND DIAGRAMS .................................................................................249
36.1 MULTIPLEXED BUS AC CHARACTERISTICS ............................................................................................249 FIGURE 36-1. INTEL BUS READ TIMING (BTS = 0/MUX = 1) ..............................................................................250 FIGURE 36-2. INTEL BUS WRITE TIMING (BTS = 0/MUX = 1) ............................................................................250 FIGURE 36-3. MOTOROLA BUS TIMING (BTS = 1/MUX = 1)...............................................................................251 36.2 NONMULTIPLEXED BUS AC CHARACTERISTICS .....................................................................................252 FIGURE 36-4. INTEL BUS READ TIMING (BTS = 0/MUX = 0) ..............................................................................253 FIGURE 36-5. INTEL BUS WRITE TIMING (BTS = 0/MUX = 0) ............................................................................253 FIGURE 36-6. MOTOROLA BUS READ TIMING (BTS = 1/MUX = 0).....................................................................254 FIGURE 36-7. MOTOROLA BUS WRITE TIMING (BTS = 1/MUX = 0)...................................................................254 36.3 RECEIVE-SIDE AC CHARACTERISTICS ....................................................................................................255 FIGURE 36-9. RECEIVE-SIDE TIMING, ELASTIC STORE ENABLED ........................................................................257 FIGURE 36-10. RECEIVE LINE INTERFACE TIMING ...............................................................................................257 36.4 TRANSMIT AC CHARACTERISTICS ..........................................................................................................258 FIGURE 36-11. TRANSMIT-SIDE TIMING ...............................................................................................................259 FIGURE 36-12. TRANSMIT-SIDE TIMING, ELASTIC STORE ENABLED....................................................................260 FIGURE 36-13. TRANSMIT LINE INTERFACE TIMING ............................................................................................260 36.5 UTOPIA TRANSMIT AC CHARACTERISTICS ..........................................................................................261 36.6 UTOPIA RECEIVE AC CHARACTERISTICS .............................................................................................261 FIGURE 36-14. UTOPIA INTERFACE SETUP AND HOLD TIMES............................................................................261 FIGURE 36-15. UTOPIA INTERFACE DELAY TIMES .............................................................................................261 37. 37.1 MECHANICAL DESCRIPTION ............................................................................................................262 LQFP (L) PACKAGE ................................................................................................................................262
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DS2156
1. MAIN FEATURES
The DS2156 contains all of the features of the previous generation of Dallas Semiconductor's T1 and E1 SCTs plus many new features such as a UTOPIA bus interface. General Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation 8-bit parallel control port, multiplexed or nonmultiplexed, Intel or Motorola IEEE 1149.1 JTAG-Boundary Scan 3.3V supply with 5V tolerant inputs and outputs Pin compatible with DS2155, DS2152/DS2154, and DS21x5Y SCT family Signaling System 7 Support RAI-CI, AIS-CI support 100-pin LQFP package (14mm x 14mm) (DS2156) 3.3V supply with 5V tolerant inputs and outputs LQFP package that is pin compatible with DS2152/DS2154, DS21352/DS21354, DS21552/DS21554, and DS2155 Evaluation kits IEEE 1149.1 JTAG boundary scan Driver source code available from the factory Line Interface Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Fully software configurable Short-haul and long-haul applications Automatic receive sensitivity adjustments Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1 applications Receive level indication in 2.5dB steps from -42.5dB to -2.5dB Internal receive termination option for 75, 100, and 120 lines Internal transmit termination option for 75, 100, and 120 lines Monitor application gain settings of 20dB, 26dB, and 32dB G.703 receive synchronization-signal mode Flexible transmit waveform generation T1 DSX-1 line buildouts T1 CSU line buildouts of -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75 coax and 120 twisted cables AIS generation independent of loopbacks Alternating ones and zeros generation Square-wave output Open-drain output option
NRZ format option Transmitter power-down Transmitter 50mA short-circuit limiter with current-limit-exceeded indication Transmit open-circuit-detected indication Line interface function can be completely decoupled from the framer/formatter
Clock Synthesizer Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz Derived from recovered receive clock Jitter Attenuator 32-bit or 128-bit crystal-less jitter attenuator Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats include D4 (SLC-96) and ESF Detailed alarm and status reporting with optional interrupt support Large path and line error counters for: - T1: BPV, CV, CRC6, and framing bit errors - E1: BPV, CV, CRC4, E-bit, and frame alignment errors Timed or manual update modes DS1 idle code generation on a per-channel basis in both transmit and receive paths - User-defined - Digital milliwatt ANSI T1.403-1998 Support RAI-CI detection and generation AIS-CI detection and generation E1ETS 300 011 RAI generation G.965 V5.2 link detect Ability to monitor one DS0 channel in both the transmit and receive paths In-band repeating pattern generators and detectors - Three independent generators and detectors - Patterns from 1 to 8 bits or 16 bits in length RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state 8 of 262
DS2156

Flexible signaling support - Software or hardware based - Interrupt generated on change of signaling data - Receive signaling freeze on loss-of-sync, carrier loss, or frame slip Addition of hardware pins to indicate carrier loss and signaling freeze Automatic RAI generation to ETS 300 011 specifications Access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support - Ability to calculate and check CRC6 according to the Japanese standard - Ability to generate Yellow Alarm according to the Japanese standard

TDM Bus Dual two-frame independent receive and transmit elastic stores - Independent control and clocking - Controlled slip capability with status - Minimum delay mode supported 16.384MHz maximum backplane burst rate Supports T1 to CEPT (E1) conversion Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation Hardware signaling capability - Receive signaling reinsertion to a backplane multiframe sync - Availability of signaling in a separate PCM data stream - Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode Access to the data streams in between the framer/formatter and the elastic stores User-selectable synthesized clock output UTOPIA Bus Supports fractional T1/E1 and arbitrary bit rates in multiples of 64kbps (DS0/TS) up to 2.048Mbps Supports clear E1 Compliant to the ATM forum specifications for ATM over DS1 and E1, respectively Standard UTOPIA-II interface to the ATM layer Configurable UTOPIA address Supports diagnostic loopback Optional payload scrambling in transmit direction and descrambling in receive direction as per the ITU I.432 for the cell-based physical layer Optional HEC insertion in transmit direction with programmable COSET polynomial addition
Option of using either idle or unassigned cells for cell-rate decoupling in transmit direction 1-Byte programmable pattern for payload of cells used for cell-rate decoupling Transmit FIFO depth configurable to either 2, 3, 4 cell deep, which provides control over cell latency Transmit FIFO depth indication for 2-cell space Optional single-bit HEC error insertion HEC-based cell delineation Optional single-bit HEC error correction in the receive direction Optional filtering of HEC errored cells received Optional receive idle/unassigned cell filtering Programmable loss-of-cell delineation (LCD) integration and optional interrupt Interrupt for FIFO overrun in receive direction Saturating counts for: - Number of error-free assigned cells received and transmitted - Number of correctable and uncorrectable HECerrored cells received Optional internally generated clock (system clock divided by 8) in diagnostic loopback mode
HDLC Controllers Two independent HDLC controllers Fast load and unload features for FIFOs SS7 support for FISU transmit and receive Independent 128-byte Rx and Tx buffers with interrupt support Access FDL, Sa, or single/multiple DS0 channels DS0 access includes Nx64 or Nx56 Compatible with polled or interrupt driven environments Bit-oriented code (BOC) support Test and Diagnostics Programmable on-chip bit error-rate testing Pseudorandom patterns including QRSS User-defined repetitive patterns Daly pattern Error insertion single and continuous Total bit and errored bit counts Payload error insertion Error insertion in the payload portion of the T1 frame in the transmit path Errors can be inserted over the entire frame or selected channels Insertion options include continuous and absolute number with selectable insertion rates F-bit corruption for line testing Loopbacks: remote, local, analog, and per-channel loopback 9 of 262
DS2156 Extended System Information Bus Host can read interrupt and alarm status on up to 8 ports with a single bus read User-Programmable Output Pins Four user-defined output pins for controlling external logic Control Port 8-bit parallel control port Multiplexed or nonmultiplexed buses Intel or Motorola formats Supports polled or interrupt environments Software access to device ID and silicon revision Software reset supported - Automatic clear on power-up Hardware reset pin
The DS2156 is compliant with the following standards: ANSI: AT&T: ITU: ITU-T: ETSI: Japanese: ATM Forum: ATM Forum: ATM Forum: T1.403-1995, T1.231-1993, T1.408 TR54016, TR62411 G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161 Recommendation I.432-03/93 B-ISDN User-Network Interface--Physical Layer Specification ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4 JTG.703, JTI.431, JJ-20.11 (CMI Coding Only) "DS1 Physical Layer Specification," af-phy-0016.000, September 1994 "E1 Physical Layer Specification," af-phy-0064.000, September 1996 "UTOPIA Level 2 Specification," Version 1.0, af-phy-0039.000, June 1995
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2. DETAILED DESCRIPTION
The DS2156 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and longhaul applications. The backplane is user-configurable for a TDM or UTOPIA II bus interface. The DS2156 is composed of an LIU, framer, HDLC controllers, and a UTOPIA/TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2156 is pin and software compatible with the DS2155. The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line buildouts as well as CSU line buildouts of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75 coax and 120 twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for interfacing to optical networks. On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane interface section. Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data through the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus reducing the amount of processor overhead required to manage the flow of data. In addition, built-in support for reducing the processor time is required in SS7 applications. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers to share a high-speed backplane in TDM mode. The parallel port provides access for control and configuration of the DS2156's features. The extended system information bus (ESIB) function allows up to eight transceivers to be accessed by a single read for interrupt status or other user-selectable alarm status information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.
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Reader's Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125ms frame there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of eight bits that are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The term "locked" is used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations are used: B8ZS BOC CRC D4 ESF FDL FPS Fs Ft HDLC MF SLC-96 Bipolar with 8 Zero Substitution Bit-Oriented Code Cyclical Redundancy Check Superframe (12 frames per multiframe) Multiframe Structure Extended Superframe (24 frames per multiframe) Multiframe Structure Facility Data Link Framing Pattern Sequence in ESF Signaling Framing Pattern in D4 Terminal Framing Pattern in D4 High-Level Data Link Control Multiframe Subscriber Loop Carrier--96 Channels
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2.1
Block Diagram
Figure 2-1 shows a simplified block diagram featuring the major components of the DS2156. Details are shown in subsequent figures. About 30 device pins have dual functions depending on the selection of the backplane, UTOPIA, or TDM. Some of the block diagrams depict a configuration based on the state of the backplane selection. The block diagram is divided into three functional blocks: LIU, FRAMER, and BACKPLANE INTERFACE.
Figure 2-1. Block Diagram
CLOCK
CLOCK ADAPTER
EXTERNAL ACCESS TO RECEIVE SIGNALS (TDM BACKPLANE ONLY)
REMOTE LOOPBACK
JITTER ATTENUATOR
LOCAL LOOPBACK
FRAMER LOOPBACK
TX LIU
MUX
FRAMER SINGALING ALARM GEN HDLCs CRC GEN HDB3 / B8ZS
BACKPLANE INTERFACE CIRCUIT UTOPIA or TDM
LIU
EXTERNAL ACCESS TO TRANSMIT SIGNALS (TDM BACKPLANE ONLY)
FRAMER
ESIB
BACKPLANE INTERFACE
JTAG
HOST INTERFACE
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BACKPLANE
RX LIU T1/E1/J1 NETWORK
MUX
PAYLOAD LOOPBACK
HDB3 / B8ZS SYNC SINGALING ALARM DET HDLCs
BACKPLANE CLOCK SYNTH
DS2156
JACLK RPOS RNEG RCLK
Figure 2-2. Receive and Transmit LIU (TDM Backplane Enabled)
RCL
REMOTE LOOPBACK RPOSI MUX RCLKI RNEGI RNEGO RCLKO RPOSO JITTER ATTENUATOR TRANSMIT OR RECEIVE PATH
32.768MHz
TPOS TNEG TCLK
TPOSO TCLKO TNEGO MUX TNEGI TCLKI TPOSI LIUC
XTALD MCLK
VCO / PLL
8XCLK
LOCAL LOOPBACK
RECEIVE LINE I/F
TRANSMIT LINE I/F
RRING
TRING
RTIP
TTIP
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Figure 2-3. Receive and Transmit LIU (UTOPIA Backplane Enabled)
8XCLK
XTALD
32.768MHz
MCLK RECEIVE LINE I/F
RCL JACLK
VCO / PLL
REMOTE LOOPBACK
RRING RTIP
RPOS RNEG RCLK
JITTER ATTENUATOR TRANSMIT OR RECEIVE PATH
LOCAL LOOPBACK
TRANSMIT LINE I/F
TRING TTIP
TPOS TNEG TCLK
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Figure 2-4. Receive and Transmit Framer/HDLC
REC HDLC #1 128 Byte FIFO DATA MAPPER
REC HDLC #2 128 Byte FIFO MAPPER
RPOS RNEG RCLK
DATA PAYLOAD LOOPBACK CLOCK SYNC SYNC CLOCK DATA
RECEIVE FRAMER
CLOCK SYNC SYNC
FRAMER LOOPBACK
TPOS TNEG TCLK
TRANSMIT FRAMER
CLOCK DATA
MAPPER
MAPPER
XMIT HDLC #1 128 Byte FIFO
XMIT HDLC #2 128 Byte FIFO
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Figure 2-5. Backplane Interface (TDM Backplane Enabled)
Sa BIT/FDL EXTRACTION
RLINK RLCLK RSIG RSIGFR
SIGNALING BUFFER
DATA CLOCK SYNC
ELASTIC STORE
RSYSCLK RSER RCLK RSYNC RMSYNC RFSYNC RDATA
CHANNEL TIMING
RCHCLK RCHBLK
SYNC DATA CLOCK Sa/FDL INSERT ELASTIC STORE
SIGNALING BUFFER
TSER TSIG TSSYNC TSYSCLK TSYNC
TESO TDATA TLCLK TLINK CHANNEL TIMING TCLK MUX TCHCLK TCHBLK TCLK
JACLK
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Figure 2-6. Backplane Interface (UTOPIA Bus Enabled)
RCLK RCHCLK RECEIVE FRAMER INTERFACE CONTROL SCRAMBLING & RATE DECOUPLING CELL STORAGE FIFO RECEIVE UTOPIA BUS INTERFACE
5 8
RSYNC RDATA RCLK UR-ENB UR-SOC UR-CLK UR-CLAV0 UR-ADDR0 TO UR-ADDR4 UR-DATA0 TO UR-DATA7
DATA
SYNC LOOPBACK
TCHCLK
DATA
DATA
TRANSMIT FRAMER INTERFACE
CONTROL SCRAMBLING & RATE DECOUPLING
CELL STORAGE FIFO
TRANSMIT UTOPIA BUS INTERFACE
5 8
UT-ENB UT-SOC UT-CLK UT-CLAV0 UT-2CLAV0 UT-ADDR0 TO UT-ADDR4 UT-DATA0 TO UT-DATA7 TCLK UT-UTDO TSYNC TDATA
SYNC
TCLK
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3. PIN FUNCTION DESCRIPTION
The DS2156 has a user-selectable TDM or UTOPIA backplane. Table 3-A and Table 3-B indicate which pins have alternate functions depending on the backplane selected. Note that even when the UTOPIA backplane is selected, the basic TDM signals such as clock, data, and frame-sync are available for both the transmit and receive directions.
3.1
TDM Backplane
3.1.1 Transmit Side
Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544MHz (T1) or a 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter. TCLK can be internally sourced from MCLK. This is the most flexible method and requires only a single clock signal for both T1 or E1. If internal sourcing is used, then the TCLK pin should be connected low. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. Signal Name: TCHCLK Signal Description: Transmit Channel Clock Signal Type: Output A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated transmit bit clock on a per-channel basis. Synchronous with TCLK when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallelto-serial conversion of channel data. Signal Name: TCHBLK Signal Description: Transmit Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. Signal Name: TSYSCLK Signal Description: Transmit System Clock Signal Type: Input 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store function is enabled. Should be connected low in applications that do not use the transmit-side elastic store. See Section 28 for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.
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DS2156 Signal Name: TLCLK Signal Description: Transmit Link Clock Signal Type: Output Demand clock for the transmit link data [TLINK] input. T1 Mode: A 4kHz or 2kHz (ZBTSI) clock. E1 Mode: A 4kHz to 20kHz clock. Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin is sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4), or the Z-bit position (ZBTSI) or any combination of the Sa-bit positions (E1). Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set by IOCR1.3 to output double-wide pulses at signaling frames in T1 mode. Signal Name: TSSYNC Signal Description: Transmit System Sync Signal Type: Input Only used when the transmit-side elastic store is enabled. A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. Should be connected low in applications that do not use the transmit-side elastic store. Signal Name: TSIG Signal Description: Transmit Signaling Input Signal Type: Input When enabled, this input samples signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. Signal Name: TESO Signal Description: Transmit Elastic Store Data Output Signal Type: Output Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic store is enabled or not. This pin is normally connected to TDATA. Signal Name: TDATA Signal Description: Transmit Data Signal Type: Input Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This pin is normally connected to TESO.
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Signal Name: TPOSO Signal Description: Transmit Positive-Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data by the output data format (IOCR1.0) control bit. This pin is normally connected to TPOSI. Signal Name: TNEGO Signal Description: Transmit Negative-Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally connected to TNEGI. Signal Name: TCLKO Signal Description: Transmit Clock Output Signal Type: Output Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin is normally connected to TCLKI. Signal Name: TPOSI Signal Description: Transmit Positive-Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications. Signal Name: TNEGI Signal Description: Transmit Negative-Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications. Signal Name: TCLKI Signal Description: Transmit Clock Input Signal Type: Input Line interface transmit clock. Can be internally connected to TCLKO by connecting the LIUC pin high.
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3.1.2 Receive Side
Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output. E1 Mode: A 4kHz to 20kHz clock. Signal Name: RCLK Signal Description: Receive Clock Signal Type: Output 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer. Signal Name: RCHCLK Signal Description: Receive Channel Clock Signal Type: Output A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data. Signal Name: RCHBLK Signal Description: Receive Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 17 for details. Signal Name: RSER Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin that identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output frame boundaries, then through IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input through IOCR1.4, at which a frame or multiframe boundary pulse is applied. Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. 22 of 262
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Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is output at this pin that identifies multiframe boundaries. Signal Name: RDATA Signal Description: Receive Data Signal Type: Output Updated on the rising edge of RCLK with the data out of the receive-side framer. Signal Name: RSYSCLK Signal Description: Receive System Clock Signal Type: Input 1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store function is enabled. Should be connected low in applications that do not use the receive-side elastic store. See Section 28 for details on 4.096MHz and 8.192MHz operation using the IBO. Signal Name: RSIG Signal Description: Receive Signaling Output Signal Type: Output Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. Signal Name: RLOS/LOTC Signal Description: Receive Loss-of-Sync/Loss-of-Transmit Clock Signal Type: Output A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5ms. Signal Name: RCL Signal Description: Receive Carrier Loss Signal Type: Output Set high when the line interface detects a carrier loss. Signal Name: RSIGF Signal Description: Receive Signaling Freeze Signal Type: Output Set high when the signaling data is frozen by either automatic or manual intervention. Used to alert downstream equipment of the condition. Signal Name: BPCLK Signal Description: Backplane Clock Signal Type: Output A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
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Signal Name: RPOSO Signal Description: Receive Positive-Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally connected to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative-Data Output Signal Type: Output Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally connected to RPOSI. Signal Name: RCLKO Signal Description: Receive Clock Output Signal Type: Output Buffered recovered clock from the network. This pin is normally connected to RCLKI. Signal Name: RPOSI Signal Description: Receive Positive-Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be connected together for an NRZ interface. Can be internally connected to RPOSO by connecting the LIUC pin high. Signal Name: RNEGI Signal Description: Receive Negative-Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be connected together for an NRZ interface. Can be internally connected to RNEGO by connecting the LIUC pin high. Signal Name: RCLKI Signal Description: Receive Clock Input Signal Type: Input Clock used to clock data through the receive-side framer. This pin is normally connected to RCLKO. Can be internally connected to RCLKO by connecting the LIUC pin high.
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3.2
UTOPIA Bus
3.2.1 Receive Side
Signal Name: UR-ADDR0 to UR-ADDR4 Signal Description: Receive UTOPIA Address Signal Type: Input 5-bit UTOPIA address bus driven from ATM layer to select the appropriate UTOPIA port. RX_UTOP_ADDR4 is the MSB; RX_UTOP_ADDR0 is the LSB. Signal Name: UR-ENB Signal Description: Receive UTOPIA Enable Signal Type: Input Active-low signal asserted by the ATM layer to indicate that UR-DATAx and UR-SOC are sampled at the end of the next cycle. Signal Name: UR-SOC Signal Description: Receive UTOPIA Start of Cell Signal Type: Output Active-high signal asserted by the DS2156 when UR-DATAx contains the first valid byte of a cell and is enabled only in cycles following those with UR-ENB asserted and cell transfer is in progress. Signal Name: UR-DATA0 to UR-DATA7 Signal Description: Receive UTOPIA Data Bus Signal Type: Output This byte-wide data bus is driven by the DS2156 in response to the selection of one of the UTOPIA ports by the ATM layer for cell transfer. This bus is tri-statable and is enabled only in cycles following those with UR-ENB asserted and cell transfer is in progress for a port. UR-DATA7 is the MSB; UR-DATA0 is the LSB. Signal Name: UR-CLAV Signal Description: Receive UTOPIA Cell Available Signal Type: Output The active-high UR-CLAV signal is asserted if a complete cell is available for transfer to the ATM layer for the polled port. If UR-ADDRx does not match with any one of UTOPIA port addresses, this signal is three-stated at the chip level using the control lines detailed below. UR-CLAV0 is driven in multiplexed bus with 1CLAV polling mode as well as direct status mode. Signal Name: UR-CLK Signal Description: Receive UTOPIA Clock Signal Type: Input Receive UTOPIA bus clock.
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3.2.2 Transmit Side
Signal Name: UT-ADDR0 to UT-ADDR4 Signal Description: Transmit UTOPIA Address Signal Type: Input This 5-bit wide bus is driven by the ATM layer to poll and select the appropriate UTOPIA port. UT-ADDR4 is the MSB; UT-ADDR0 is the LSB. Signal Name: UT-ENB Signal Description: Transmit UTOPIA Enable Signal Type: Input Active-low enable signal asserted by ATM layer during cycles when UT-DATAx contains valid cell data. Signal Name: UT-SOC Signal Description: Transmit UTOPIA Start of Cell Signal Type: Input Active-high signal asserted by ATM layer when UT-DATAx contains the first valid byte of the cell. Signal Name: UT-DATA0 to UT-DATA7 Signal Description: Transmit UTOPIA Data Bus Signal Type: Input Byte-wide true data driven from ATM layer to one of the selected ports. UT-DATA7 is the MSB; UT-DATA0 is the LSB. Signal Name: UT-CLAV Signal Description: Transmit UTOPIA Cell Available Signal Type: Output This active-high UT-CLAV signal is asserted by the DS2156 if it has a cell space available to accommodate a complete cell from the ATM layer to the polled port. Signal Name: UT-2CLAV Signal Description: Transmit UTOPIA 2 Cells Available Signal Type: Output This active-high signal is asserted by the DS2156 to indicate that the transmitter can accommodate two cells. UT2CLAV0 is driven in multiplexed bus with 1CLAV mode as well as direct status mode for port 0. The timing of this signal follows as that of UT-CLAV. This bus is not tri-statable. Signal Name: UT-UTDO Signal Description: UTOPIA Transmit Data Output Signal Type: Output Access to the data prior to the transmit formatter. Updated on the rising edge of TCLK. This output is normally connected to TDATA. Signal Name: UT-CLK Signal Description: Receive UTOPIA Clock Signal Type: Input Transmit UTOPIA bus clock.
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3.3
Parallel Control Port Pins
Signal Name: INT Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output. Signal Name: TSTRST Signal Description: Three-State Control and Device Reset Signal Type: Input A dual function pin. A 0-to-1 transition issues a hardware reset to the DS2156 register set. A reset clears all configuration registers. Configuration register contents are set to 0. Leaving TSTRST high three-states all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: AD0 to AD7 Signal Description: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), these serve as the data bus. In multiplexed bus operation (MUX = 1), these pins serve as an 8-bit multiplexed address/data bus. Signal Name: A0 to A6 Signal Description: Address Bus Signal Type: Input In nonmultiplexed bus operation (MUX = 0), these serve as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be connected low. Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, then these pins assume the function listed in parentheses (). Signal Name: RD (DS) Signal Description: Read Input, Data Strobe Signal Type: Input RD and DS are active-low signals. DS active HIGH when MUX = 1. See Bus Timing Diagrams.
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DS2156 Signal Name: CS Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS is an active-low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable (Address Strobe) or A7 Signal Type: Input In nonmultiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus on a positive-going edge. Signal Name: WR (R/W) Signal Description: Write Input(Read/Write) Signal Type: Input WR is an active-low signal. Signal Name: TUSEL Signal Description: TDM/UTOPIA Backplane Select Signal Type: Input Low to enable TDM backplane. High to enable UTOPIA backplane.
3.4
Extended System Information Bus
Signal Name: ESIBS0 Signal Description: Extended System Information Bus Select 0 Signal Type: Input/Output Used to group two to eight DS2156s into a bus-sharing mode for alarm and status reporting. See Section 29 for more details. Signal Name: ESIBS1 Signal Description: Extended System Information Bus Select 1 Signal Type: Input/Output Used to group two to eight DS2156s into a bus-sharing mode for alarm and status reporting. See Section 29 for more details. Signal Name: ESIBRD Signal Description: Extended System Information Bus Read Signal Type: Input/Output Used to group two to eight DS2156s into a bus-sharing mode for alarm and status reporting. See Section 29 for more details.
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3.5
User Output Port Pins
Signal Name: UOP0 Signal Description: User Output Port 0 Signal Type: Output This output port pin can be set low or high by the CCR4.0 control bit. This pin is forced low on power-up and after any device reset. Signal Name: UOP1 Signal Description: User Output Port 1 Signal Type: Output This output port pin can be set low or high by the CCR4.1 control bit. This pin is forced low on power-up and after any device reset. Signal Name: UOP2 Signal Description: User Output Port 2 Signal Type: Output This output port pin can be set low or high by the CCR4.2 control bit. This pin is forced low on power-up and after any device reset. Signal Name: UOP3 Signal Description: User Output Port 3 Signal Type: Output This output port pin can be set low or high by the CCR4.3 control bit. This pin is forced low on power-up and after any device reset.
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3.6
JTAG Test Access Port Pins
JTRST IEEE 1149.1 Test Reset Input
Signal Name: Signal Description: Signal Type:
JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST low. JTRST is pulled high internally by a 10k resistor operation. Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k pullup resistor. Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor. Signal Name: JTDO Signal Description: IEEE 1149.1 Test Data Output Signal Type: Output Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.
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3.7
Line Interface Pins
MCLK
Signal Name:
Signal Description: Signal Type:
Master Clock Input Input
A (50ppm) clock source is applied at this pin. This clock is used internally for both clock/data recovery and for the jitter attenuator for T1 and E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS2156 in T1-only operation, a 1.544MHz (50ppm) clock source can be used. Signal Name: XTALD
Signal Description: Signal Type:
Quartz Crystal Driver Output
A quartz crystal of 2.048MHz (optional 1.544MHz in T1-only operation) can be applied across MCLK and XTALD instead of a clock source at MCLK. Leave open circuited if a clock source is applied at MCLK. Signal Name: 8XCLK
Signal Description: Eight Times Clock (8x) Signal Type: Output An 8x clock that is locked to the recovered network clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side).
Signal Name: LIUC
Signal Description: Signal Type:
Line Interface Connect Input
Connect low to separate the line interface circuitry from the framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Connect high to connect the line interface circuitry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is connected high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be connected low. Signal Name: RTIP and RRING
Signal Description: Signal Type:
Receive Tip and Ring Input
Analog inputs for clock recovery circuitry. These pins connect through a 1:1 transformer to the network. See Section 23 for details. Signal Name: TTIP and TRING
Signal Description: Signal Type:
Transmit Tip and Ring Output
Analog line driver outputs. These pins connect through a 1:2 step-up transformer to the network. See Section 23 for details.
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DS2156
3.8
Supply Pins
Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V 5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V 5%. Should be connected to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 3.3V 5%. Should be connected to the RVDD and DVDD pins. Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply Should be connected to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0V. Should be connected to DVSS and TVSS. Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0V. Should be connected to DVSS and RVSS.
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3.9
L and G Package Pinout
The DS2156 is available in either a 100-pin LQFP (L) or 10mm CSBGA, 0.8mm pitch (G) package.
Table 3-A. Pin Description Sorted by Pin Number (TDM Backplane Enabled)
BOLD entries indicate pins that have an alternate function when UTOPIA bus interface is enabled.
PIN LQFP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19, 20, 24 21 22 23 25 26 27, 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44, 61, 81, 83 45, 60, 80, 84 46 47 48
CSBGA
A1 B2 C3 B1 D4 C2 C1 D3 D2 D1 E3 E2 E1 E4 E5 F1 F2 F3 F4, G1, J1 G2 H1 G3 H2 K1 J2, H3 K2 G4 J3 K3 H4 J4 K4 H5 J5 K5 G5 F5 K6 J6 H6 K7, F8, B8, C7 G6, G10, D7, B7 J7 K8 H7
SYMBOL
RCHBLK JTMS BPCLK JTCLK JTRST RCL JTDI UOP0 UOP1 JTDO BTS LIUC 8XCLK TSTRST UOP2 RTIP RRING RVDD RVSS MCLK XTALD UOP3 INT TUSEL N.C. TTIP TVSS TVDD TRING TCHBLK TLCLK TLINK ESIBS0 TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO DVDD DVSS TCLK TSER TSIG
TYPE
O I O I I O I O O O I I O I O I I -- -- I O O O -- -- O - - O O O I I/O I/O I I I O O O -- -- I I I
FUNCTION
Receive Channel Block IEEE 1149.1 Test Mode Select Backplane Clock IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Reset Receive Carrier Loss IEEE 1149.1 Test Data Input User Output 0 User Output 1 IEEE 1149.1 Test Data Output Bus Type Select Line Interface Connect Eight Times Clock Test/Reset User Output 2 Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Receive Analog Signal Ground Master Clock Input Quartz Crystal Driver User Output 3 Interrupt Backplane Interface Select Reserved for Factory Test Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Channel Block Transmit Link Clock Transmit Link Data Extended System Information Bus 0 Transmit Sync Transmit Positive-Data Input Transmit Negative-Data Input Transmit Clock Input Transmit Clock Output Transmit Negative-Data Output Transmit Positive-Data Output Digital Positive Supply Digital Signal Ground Transmit Clock Transmit Serial Data Transmit Signaling Input
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DS2156 PIN LQFP
49 50 51 52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 82 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
CSBGA
K9 J8 K10 J9 H8 J10 G7 H9 H10 G8 G9 F9 F10 F7 F6 E10 E9 E8 D10 E7 D9 C10 D8 B10 C9 A10 B9 C8 A9 A8 A7 C6 B6 A6 D6 E6 A5 B5 C5 A4 D5 B4 A3 C4 A2 B3
SYMBOL
TESO TDATA TSYSCLK TSSYNC TCHCLK ESIBS1 MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 RD (DS) CS ESIBRD WR (R/W) RLINK RLCLK RCLK RDATA RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF RSIG RSER RMSYNC RFSYNC RSYNC RLOS/LOTC RSYSCLK
TYPE
O I I I O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I/O I O O O O I I I O O O O O O O O O I/O O I
FUNCTION
Transmit Elastic Store Output Transmit Data Transmit System Clock Transmit System Sync Transmit Channel Clock Extended System Information Bus 1 Bus Operation Data Bus Bit0/Address/Data Bus Bit 0 Data Bus Bit1/Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus 2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Latch Enable/Address Bus Bit 7 Read Input (Data Strobe) Chip Select Extended System Information Bus Read Write Input (Read/Write) Receive Link Data Receive Link Clock Receive Clock Receive Data Receive Positive-Data Input Receive Negative-Data Input Receive Clock Input Receive Clock Output Receive Negative-Data Output Receive Positive-Data Output Receive Channel Clock Receive Signaling-Freeze Output Receive Signaling Output Receive Serial Data Receive Multiframe Sync Receive Frame Sync Receive Sync Receive Loss-of-Sync/Loss-of-Transmit Clock Receive System Clock
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Table 3-B. Pin Description Sorted by Pin Number (UTOPIA Backplane Enabled)
BOLD entries indicate pins that have an alternate function when the TDM bus interface is enabled.
PIN LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19, 20, 24 21 22 23 25 26 27, 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44, 61, 81, 83 45, 60, 80, 84 46 47 48 CSBGA A1 B2 C3 B1 D4 C2 C1 D3 D2 D1 E3 E2 E1 E4 E5 F1 F2 F3 F4, G1, J1 G2 H1 G3 H2 K1 J2, H3 K2 G4 J3 K3 H4 J4 K4 H5 J5 K5 G5 F5 K6 J6 H6 K7, F8, B8, C7 G6, G10, D7, B7 J7 K8 H7
SYMBOL UR-SOC JTMS UR-ENB JTCLK JTRST RCL JTDI UT-SOC UT-ENB JTDO BTS UT-CLAV 8XCLK TSTRST UOP2 RTIP RRING RVDD RVSS MCLK XTALD UT-ADDR0 INT TUSEL N.C. TTIP TVSS TVDD TRING UT-ADDR1 UT-ADDR2 UT-ADDR3 ESIBS0 TSYNC UT-ADDR4 UT-DATA0 UT-DATA1 UT-DATA2 UT-DATA3 UT-DATA4 DVDD DVSS TCLK UT-DATA5 UT-DATA6
TYPE O I I I I O I I I O I O O I I I -- -- I O I O I -- O -- -- O I I I I/O I/O I I I I I I -- -- I I I
DESCRIPTION UTOPIA Receive Start of Cell IEEE 1149.1 Test Mode Select UTOPIA Receive Enable IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Reset Receive Carrier Loss IEEE 1149.1 Test Data Input UTOPIA Transmit Start of Cell UTOPIA Transmit Enable IEEE 1149.1 Test Data Output Bus Type Select UTOPIA Transmit Cell Available Eight Times Clock Test/Reset User Output Pin 2 Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Receive Analog Signal Ground Master Clock Input Quartz Crystal Driver UTOPIA Transmit Address Bus Bit 0 Interrupt Backplane Interface Select No Connection. Reserved for Factory Test Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output UTOPIA Transmit Address Bus Bit 1 UTOPIA Transmit Address Bus Bit 2 UTOPIA Transmit Address Bus Bit 3 Extended System Information Bus 0 Transmit Sync UTOPIA Transmit Address Bus Bit 4 UTOPIA Transmit Data Bus Bit 0 UTOPIA Transmit Data Bus Bit 1 UTOPIA Transmit Data Bus Bit 2 UTOPIA Transmit Data Bus Bit 3 UTOPIA Transmit Data Bus Bit 4 Digital Positive Supply Digital Signal Ground Transmit Clock UTOPIA Transmit Data Bus Bit 5 UTOPIA Transmit Data Bus Bit 6
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PIN LQFP 49 50 51 52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 82 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 CSBGA K9 J8 K10 J9 H8 J10 G7 H9 H10 G8 G9 F9 F10 F7 F6 E10 E9 E8 D10 E7 D9 C10 D8 B10 C9 A10 B9 C8 A9 A8 A7 C6 B6 A6 D6 E6 A5 B5 C5 A4 D5 B4 A3 C4 A2 B3 SYMBOL UT-UTDO TDATA UT-DATA7 UT-CLK UR-CLK ESIBS1 MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 RD (DS) CS ESIBRD WR (R/W) UR-DATA0 UR-DATA1 RCLK RDATA UR-DATA2 UR-DATA3 UR-DATA4 UR-DATA5 UR-DATA6 UR-DATA7 UR-ADDR0 UR-ADDR1 UR-ADDR2 UR-CLAV UR-ADDR3 UR-ADDR4 RSYNC RLOS/LOTC UT-2CLAV TYPE O I I I I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I/O I O O O O O O O O O O I I I O I I I/O O O DESCRIPTION UTOPIA Transmit Data Output Transmit Data UTOPIA Transmit Data Bus Bit 7 UTOPIA Transmit Clock UTOPIA Receive Clock Extended System Information Bus 1 Bus Operation Data Bus Bit0/Address/Data Bus Bit 0 Data Bus Bit1/Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus 2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Latch Enable/Address Bus Bit 7 Read Input (Data Strobe) Chip Select Extended System Information Bus Read Write Input (Read/Write) UTOPIA Receive Data Bus Bit 0 UTOPIA Receive Data Bus Bit 1 Receive Clock Receive Data UTOPIA Receive Data Bus Bit 2 UTOPIA Receive Data Bus Bit 3 UTOPIA Receive Data Bus Bit 4 UTOPIA Receive Data Bus Bit 5 UTOPIA Receive Data Bus Bit 6 UTOPIA Receive Data Bus Bit 7 UTOPIA Receive Address Bus Bit 0 UTOPIA Receive Address Bus Bit 1 UTOPIA Receive Address Bus Bit 2 UTOPIA Receive Cell Available UTOPIA Receive Address Bus Bit 3 UTOPIA Receive Address Bus Bit 4 Receive Sync Receive Loss-of-Sync/Loss-of-Transmit Clock UTOPIA Transmit 2 Cells Available
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3.10 10mm CSBGA Pin Configuration Figure 3-1. 10mm CSBGA Pin Configuration (TDM Signals Shown)
1 A B C D E F G H J K
RCHBLK
2
RLOS/ LOTC
3
RFSYNC
4
RSIG
5
RPOSO
6
RCLKI
7
RDATA
8
RCLK
9
RLCLK
10
ESIBRD
JTCLK
JTMS
RSYSCLK
RMSYNC
RCHCLK
RNEGI
DVSS
DVDD
WR (R/W)
RD (DS)
JTDI
RCL
BPCLK
RSYNC
RSIGF
RPOSI
DVDD
RLINK
CS
A6
JTDO
UOP1
UOP0
JTRST
RSER
RCLKO
DVSS
ALE(AS)/ A7
A5
A3
8XCLK
LIUC
BTS
TSTRST
UOP2
RNEGO
A4
A2
A1
A0
RTIP
RRING
RVDD
RVSS
TCLKI
D7/AD7
D6/AD6
DVDD
D4/AD4
D5/AD5
RVSS
MCLK
UOP3
TVSS
TNEGI
DVSS
MUX
D2/AD2
D3/AD3
DVSS
XTALD
INT
N.C.
TCHBLK
ESIBS0
TPOSO
TSIG
TCHCLK
D0/AD0
D1/AD1
RVSS
N.C.
TVDD
TLCLK
TSYNC
TNEGO
TCLK
TDATA
TSSYNC
ESIBS1
TUSEL
TTIP
TRING
TLINK
TPOSI
TCLKO
DVDD
TSER
TESO
TSYSCLK
TOP VIEW
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DS2156
4. PARALLEL PORT
The SCT is controlled by either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus through an external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing configurations. If the BTS pin is connected low, Intel timing is selected; if connected high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in AC Electrical Characteristics in Section 36 for more details.
4.1
Register Map
Table 4-A. Register Map Sorted by Address
ADDRESS xxh
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME
Master Mode Register I/O Configuration Register 1 I/O Configuration Register 2 T1 Receive Control Register 1 T1 Receive Control Register 2 T1 Transmit Control Register 1 T1 Transmit Control Register 2 T1 Common Control Register 1 Software Signaling Insertion Enable 1 Software Signaling Insertion Enable 2 Software Signaling Insertion Enable 3 Software Signaling Insertion Enable 4 T1 Receive Digital Milliwatt Enable Register 1 T1 Receive Digital Milliwatt Enable Register 2 T1 Receive Digital Milliwatt Enable Register 3 Device Identification Register Information Register 1 Information Register 2 Information Register 3 Interrupt Information Register 1 Interrupt Information Register 2 Status Register 1 Interrupt Mask Register 1 Status Register 2 Interrupt Mask Register 2 Status Register 3 Interrupt Mask Register 3 Status Register 4 Interrupt Mask Register 4 Status Register 5 Interrupt Mask Register 5 Status Register 6 Interrupt Mask Register 6 Status Register 7 Interrupt Mask Register 7 Status Register 8 38 of 262
SYMBOL
MSTRREG IOCR1 IOCR2 T1RCR1 T1RCR2 T1TCR1 T1TCR2 T1CCR1 SSIE1 SSIE2 SSIE3 SSIE4 T1RDMR1 T1RDMR2 T1RDMR3 IDR INFO1 INFO2 INFO3 IIR1 IIR2 SR1 IMR1 SR2 IMR2 SR3 IMR3 SR4 IMR4 SR5 IMR5 SR6 IMR6 SR7 IMR7 SR8
PAGE
48 75 76 52 53 54 55 56 99 99 100 100 58 58 58 69 59 157 66 50 50 158 159 69 70 71 72 73 74 112 112 141 142 141 142 118
DS2156
ADDRESS xxh
25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
R/W
R/W R/W R/W R/W W W W W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME
Interrupt Mask Register 8 Status Register 9 Interrupt Mask Register 9 Per-Channel Pointer Register Per-Channel Data Register 1 Per-Channel Data Register 2 Per-Channel Data Register 3 Per-Channel Data Register 4 Information Register 4 Information Register 5 Information Register 6 Information Register 7 HDLC #1 Receive Control HDLC #2 Receive Control E1 Receive Control Register 1 E1 Receive Control Register 2 E1 Transmit Control Register 1 E1 Transmit Control Register 2 BOC Control Register Receive Signaling Change-of-State Information 1 Receive Signaling Change-of-State Information 2 Receive Signaling Change-of-State Information 3 Receive Signaling Change-of-State Information 4 Receive Signaling Change-of-State Interrupt Enable 1 Receive Signaling Change-of-State Interrupt Enable 2 Receive Signaling Change-of-State Interrupt Enable 3 Receive Signaling Change-of-State Interrupt Enable 4 Signaling Control Register Error Count Configuration Register Line-Code Violation Count Register 1 Line-Code Violation Count Register 2 Path Code Violation Count Register 1 Path Code Violation Count Register 2 Frames Out-of-Sync Count Register 1 Frames Out-of-Sync Count Register 2 E-Bit Count Register 1 E-Bit Count Register 2 Loopback Control Register Per-Channel Loopback Enable Register 1 Per-Channel Loopback Enable Register 2 Per-Channel Loopback Enable Register 3 Per-Channel Loopback Enable Register 4 Elastic Store Control Register Transmit Signaling Register 1 Transmit Signaling Register 2 Transmit Signaling Register 3 Transmit Signaling Register 4 39 of 262
SYMBOL
IMR8 SR9 IMR9 PCPR PCDR1 PCDR2 PCDR3 PCDR4 INFO4 INFO5 INFO6 INFO7 H1RC H2RC E1RCR1 E1RCR2 E1TCR1 E1TCR2 BOCC RSINFO1 RSINFO2 RSINFO3 RSINFO4 RSCSE1 RSCSE2 RSCSE3 RSCSE4 SIGCR ERCNT LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 EBCR1 EBCR2 LBCR PCLR1 PCLR2 PCLR3 PCLR4 ESCR TS1 TS2 TS3 TS4
PAGE
118 204 205 45 46 46 46 46 143 143 143 66 135 135 61 62 63 64 117 94 94 94 94 94 94 94 94 91 81 83 83 84 84 85 85 86 86 77 79 79 80 80 111 97 97 97 97
DS2156
ADDRESS xxh
54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W
REGISTER NAME
Transmit Signaling Register 5 Transmit Signaling Register 6 Transmit Signaling Register 7 Transmit Signaling Register 8 Transmit Signaling Register 9 Transmit Signaling Register 10 Transmit Signaling Register 11 Transmit Signaling Register 12 Transmit Signaling Register 13 Transmit Signaling Register 14 Transmit Signaling Register 15 Transmit Signaling Register 16 Receive Signaling Register 1 Receive Signaling Register 2 Receive Signaling Register 3 Receive Signaling Register 4 Receive Signaling Register 5 Receive Signaling Register 6 Receive Signaling Register 7 Receive Signaling Register 8 Receive Signaling Register 9 Receive Signaling Register 10 Receive Signaling Register 11 Receive Signaling Register 12 Receive Signaling Register 13 Receive Signaling Register 14 Receive Signaling Register 15 Receive Signaling Register 16 Common Control Register 1 Common Control Register 2 Common Control Register 3 Common Control Register 4 Transmit Channel Monitor Select Transmit DS0 Monitor Register Receive Channel Monitor Select Receive DS0 Monitor Register Line Interface Control 1 Line Interface Control 2 Line Interface Control 3 Line Interface Control 4
SYMBOL
TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 CCR1 CCR2 CCR3 CCR4 TDS0SEL TDS0M RDS0SEL RDS0M LIC1 LIC2 LIC3 LIC4
PAGE
97 97 97 97 97 97 97 97 97 97 97 97 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 92 68 221 222 223 87 87 88 88 153 154 155 156
W R/W R/W R/W R/W
Idle Array Address Register Per-Channel Idle Code Value Register Transmit Idle Code Enable Register 1 Transmit Idle Code Enable Register 2 Transmit Idle Code Enable Register 3 40 of 262
IAAR PCICR TCICE1 TCICE2 TCICE3
104 104 105 105 105
DS2156
ADDRESS xxh
83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R R R/W R/W
REGISTER NAME
Transmit Idle Code Enable Register 4 Receive Idle Code Enable Register 1 Receive Idle Code Enable Register 2 Receive Idle Code Enable Register 3 Receive Idle Code Enable Register 4 Receive Channel Blocking Register 1 Receive Channel Blocking Register 2 Receive Channel Blocking Register 3 Receive Channel Blocking Register 4 Transmit Channel Blocking Register 1 Transmit Channel Blocking Register 2 Transmit Channel Blocking Register 3 Transmit Channel Blocking Register 4 HDLC #1 Transmit Control HDLC #1 FIFO Control HDLC #1 Receive Channel Select 1 HDLC #1 Receive Channel Select 2 HDLC #1 Receive Channel Select 3 HDLC #1 Receive Channel Select 4 HDLC #1 Receive Time Slot Bits/Sa Bits Select HDLC #1 Transmit Channel Select1 HDLC #1 Transmit Channel Select2 HDLC #1 Transmit Channel Select3 HDLC #1 Transmit Channel Select4 HDLC #1 Transmit Time Slot Bits/Sa Bits Select HDLC #1 Receive Packet Bytes Available HDLC #1 Transmit FIFO HDLC #1 Receive FIFO HDLC #1 Transmit FIFO Buffer Available HDLC #2 Transmit Control HDLC #2 FIFO Control HDLC #2 Receive Channel Select 1 HDLC #2 Receive Channel Select 2 HDLC #2 Receive Channel Select 3 HDLC #2 Receive Channel Select 4 HDLC #2 Receive Time Slot Bits/Sa Bits Select HDLC #2 Transmit Channel Select1 HDLC #2 Transmit Channel Select2 HDLC #2 Transmit Channel Select3 HDLC #2 Transmit Channel Select4 HDLC #2 Transmit Time Slot Bits/Sa Bits Select HDLC #2 Receive Packet Bytes Available HDLC #2 Transmit FIFO HDLC #2 Receive FIFO HDLC #2 Transmit FIFO Buffer Available Extend System Information Bus Control Register 1 Extend System Information Bus Control Register 2 41 of 262
SYMBOL
TCICE4 RCICE1 RCICE2 RCICE3 RCICE4 RCBR1 RCBR2 RCBR3 RCBR4 TCBR1 TCBR2 TCBR3 TCBR4 H1TC H1FC H1RCS1 H1RCS2 H1RCS3 H1RCS4 H1RTSBS H1TCS1 H1TCS2 H1TCS3 H1TCS4 H1TTSBS H1RPBA H1TF H1RF H1TFBA H2TC H2FC H2RCS1 H2RCS2 H2RCS3 H2RCS4 H2RTSBS H2TCS1 H2TCS2 H2TCS3 H2TCS4 H2TTSBS H2RPBA H2TF H2RF H2TFBA ESIBCR1 ESIBCR2
PAGE
105 106 106 106 106 107 107 108 108 109 109 109 109 134 136 137 137 137 137 138 139 139 139 139 140 144 145 145 144 134 136 137 137 137 137 138 139 139 139 139 140 144 145 145 144 218 219
DS2156
ADDRESS xxh
B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0
R/W
R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER NAME
Extend System Information Bus Register 1 Extend System Information Bus Register 2 Extend System Information Bus Register 3 Extend System Information Bus Register 4 In-Band Code Control Register Transmit Code Definition Register 1 Transmit Code Definition Register 2 Receive Up Code Definition Register 1 Receive Up Code Definition Register 2 Receive Down Code Definition Register 1 Receive Down Code Definition Register 2 In-Band Receive Spare Control Register Receive Spare Code Definition Register 1 Receive Spare Code Definition Register 2 Receive FDL Register Transmit FDL Register Receive FDL Match Register 1 Receive FDL Match Register 2 Interleave Bus Operation Control Register Receive Align Frame Register Receive Nonalign Frame Register Receive Si Align Frame Receive Si Nonalign Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Receive Sa7 Bits Receive Sa8 Bits Transmit Align Frame Register Transmit Nonalign Frame Register Transmit Si Align Frame Transmit Si Nonalign Frame Transmit Remote Alarm Bits Transmit Sa4 Bits Transmit Sa5 Bits Transmit Sa6 Bits Transmit Sa7 Bits Transmit Sa8 Bits Transmit Sa Bit Control Register BERT Alternating Word Count Rate BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Repetitive Pattern Set Register 4 BERT Control Register 1 42 of 262
SYMBOL
ESIB1 ESIB2 ESIB3 ESIB4 IBCC TCD1 TCD2 RUPCD1 RUPCD2 RDNCD1 RDNCD2 RSCC RSCD1 RSCD2 RFDL TFDL RFDLM1 RFDLM2 IBOC RAF RNAF RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 TAF TNAF TSiAF TSiNAF TRA TSa4 TSa5 TSa6 TSa7 TSa8 TSACR BAWC BRP1 BRP2 BRP3 BRP4 BC1
PAGE
220 220 220 220 194 195 195 196 196 197 197 198 199 199 147 148 147 147 215 120 120 122 123 123 124 124 125 125 126 121 121 126 127 127 128 128 129 129 130 131 205 206 206 206 206 202
DS2156
ADDRESS xxh
E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0* F1-F9* FA-FF*
R/W
R/W R R R R R R R R/W R/W R/W R/W R R -- -- --
REGISTER NAME
BERT Control Register 2 BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Interface Control Register Error Rate Control Register Number-of-Errors 1 Number-of-Errors 2 Number-of-Errors Left 1 Number-of-Errors Left 2 Test Register Test Register Test Register
SYMBOL
BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BIC ERC NOE1 NOE2 NOEL1 NOEL2 TEST TEST TEST
PAGE
203 207 207 207 207 208 208 208 209 211 212 212 213 213 -- -- --
*TEST1 to TEST16 registers are used only by the factory.
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4.2
UTOPIA Bus Registers
When the UTOPIA bus is enabled, register space 50h-6A is mapped to the UTOPIA function.
Table 4-B. UTOPIA Register Map
ADDRESS xxh 50 51 52 53 54 55 56 57 58, 59, 5A-5F 60 61 62 63 64 65 66 67 68 69 6A 6B-6F R/W R/W R/W W R R R/W R/W R/W -- R/W R/W R/W W R R R R R R R/W -- REGISTER Transmit Configuration Register Transmit PMON Counter-Latch Enable Register Transmit Assigned Cell Counter MSB Transmit Assigned Cell Counter LSB Transmit Idle/Unassigned Payload Byte Transmit HEC Error-Insertion Pattern Transmit Control Register 1 Transmit Control Register 2 Reserved Receive Configuration Register Receive LCD Integration Period Register Receive PMON Counter-Latch Enable Register Receive Correctable HEC Latch Register Receive Uncorrectable HEC MSB Receive Uncorrectable HEC LSB Receive Assigned Cell Counter MSB Receive Assigned Cell Counter LSB Receive Status Register Receive Control Register 1 Receive Control Register 2 Reserved SYMBOL U_TCFR U_TPCLE U_TACC1 U_TACC2 U_TIUPB U_THEPR U_TCR1 U_TCR2 -- U_RCFR U_RLCDIP U_RPCE U_RCHEC U_RUHEC1 U_RUHEC2 U_RACC1 U_RACC2 U_RSR U_RCR1 U_RCR2 -- PAGE 181 182 182 182 183 183 184 185 -- 185 186 186 187 187 187 188 188 189 190 191 --
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5. SPECIAL PER-CHANNEL REGISTER OPERATION
Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and perchannel data registers 1-4 (PCDR1-4). The user selects which function or functions are to be applied on a per-channel basis by setting the appropriate bit(s) in the PCPR register. The user then writes to the PCDR registers to select the channels for that function. The following is an example of mapping the transmit and receive BERT function to channels 9-12, 20, and 21. Write Write Write Write Write 11h 00h 0fh 18h 00h to to to to to PCPR PCDR1 PCDR2 PCDR3 PCDR4
The user may write to the PCDR1-4 with muliple functions in the PCPR register selected, but can only read the values from the PCDR1-4 registers for a single function at a time. More information about how to use these per-channel features can be found in their respective sections in the data sheet.
Register Name: Register Description: Register Address: Bit # Name Default 7 RSAOICS 0 PCPR Per-Channel Pointer Register 28h 6 RSRCS 0 5 RFCS 0 4 BRCS 0 3 THSCS 0 2 PEICS 0 1 TFCS 0 0 BTCS 0
Bit 0/Bert Transmit Channel Select (BTCS) Bit 1/Transmit Fractional Channel Select (TFCS) Bit 2/Payload Error Insert Channel Select (PEICS) Bit 3/Transmit Hardware Signaling Channel Select (THSCS) Bit 4/Bert Receive Channel Select (BRCS) Bit 5/Receive Fractional Channel Select (RFCS) Bit 6/Receive Signaling Reinsertion Channel Select (RSRCS) Bit 7/Receive Signaling All-Ones Insertion Channel Select (RSAOICS)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- CH8 PCDR1 Per-Channel Data Register 1 29h 6 -- CH7 5 -- CH6 4 -- CH5 3 -- CH4 2 -- CH3 1 -- CH2 0 -- CH1
Register Name: Register Description: Register Address: Bit # Name Default 7 -- CH16
PCDR2 Per-Channel Data Register 2 2Ah 6 -- CH15 5 -- CH14 4 -- CH13 3 -- CH12 2 -- CH11 1 -- CH10 0 -- CH9
Register Name: Register Description: Register Address: Bit # Name Default 7 -- CH24
PCDR3 Per-Channel Data Register 3 2Bh 6 -- CH23 5 -- CH22 4 -- CH21 3 -- CH20 2 -- CH19 1 -- CH18 0 -- CH17
Register Name: Register Description: Register Address: Bit # Name Default 7 -- CH32
PCDR4 Per-Channel Data Register 4 2Ch 6 -- CH31 5 -- CH30 4 -- CH29 3 -- CH28 2 -- CH27 1 -- CH26 0 -- CH25
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6. PROGRAMMING MODEL
The DS2156 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the DS2156, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions and enabling the common functions. The act of resetting the DS2156 automatically clears all configuration and status registers. Therefore, it is not necessary to load unused registers with 0s.
Figure 6-1. Programming Sequence
POWER-ON ISSUE RESET
SELECT T1 OR E1 OPERATION IN MASTER MODE REGISTER
PROGRAM T1 SPECIFIC REGISTERS
PROGRAM E1 SPECIFIC REGISTERS
PROGRAM COMMON REGISTERS
DS2156 OPERATIONAL
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6.1
Power-Up Sequence
The DS2156 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the DS2156. The user can issue a chip reset at any time. Issuing a reset disrupts traffic flowing through the DS2156 until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register. The LIRST (LIC2.6) should be toggled from 0 to 1 to reset the line interface circuitry. (It takes the DS2156 about 40ms to recover from the LIRST bit being toggled.) Finally, after the TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled). 6.1.1 Master Mode Register
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 MSTRREG Master Mode Register 00h 6 -- 0 5 -- 0 4 URST 0 3 TEST1 0 2 TEST0 0 1 T1/E1 0 0 SFTRST 0
Bit 0/Software-Issued Reset (SFTRST). A 0-to-1 transition causes the register space in the DS2156 to be cleared. A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed. Bit 1/DS2156 Operating Mode (T1/E1). Used to select the operating mode of the framer/formatter (digital) portion of the 2156. The operating mode of the LIU must also be programmed. 0 = T1 operation 1 = E1 operation Bits 2, 3/Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS2156 into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses. TEST1 0 0 1 1 TEST0 0 1 0 1 Effect On Output Pins Operate normally Force all output pins into three-state (including all I/O pins and parallel port pins) Force all output pins low (including all I/O pins except parallel port pins) Force all output pins high (including all I/O pins except parallel port pins)
Bit 4/UTOPIA Reset (URST). A 0-to-1 transition causes the UTOPIA interface to reset. Bits 5 to 7/Unused, must be set to 0 for proper operation
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6.2
Interrupt Handling
Various alarms, conditions, and events in the DS2156 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (status register 1) has an interrupt control register called IMR1 (interrupt mask register 1). Status registers are the only sources of interrupts in the DS2156. On power-up, all writeable registers are automatically cleared. Since bits in the IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host selects which events are to product interrupts. Since there are potentially many sources of interrupts on the DS2156, several features are available to help sort out and identify which event is causing an interrupt. When an interrupt occurs, the host should first read the IIR1 and IIR2 registers (interrupt information registers) to identify which status register (or registers) is producing the interrupt. Once that is determined, the individual status register or registers can be examined to determine the exact source. In multiple port configurations, two to eight DS2156s can be connected together by the 3-wire ESIB feature. This allows multiple DS2156s to be interrogated by a single CPU port read cycle. The host can determine the synchronization status, or interrupt status of up to eight devices with a single read. The ESIB feature also allows the user to select from various events to be examined through this method. For more information, see Section 29. The U_RSR register in the UTOPIA sections works slightly different than all other status registers. Only two of the bits in this register are capable of generating interrupts, U_RSR.0 and U_RSR.1. These two bits, unlike the other status register bits, are only set if the corresponding mask bits U_RCR2.3 and U_RCR2.4 are set. Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (CCR3.6) to stop further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt hander routine should re-enable interrupts by setting the INTDIS bit = 0.
6.3
Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit in a status register is set to a 1. All of the status registers operate in a latched fashion. This means that if an event or condition occurs a bit is set to a 1. It remains set until the user reads that bit. An event bit is cleared when it is read and it is not set again until the event has occurred again. Condition bits such as RBL, RLOS, etc., remain set if the alarm is still present. The user always proceeds a read of any of the status registers with a write. The byte written to the register informs the DS2156 which bits the user wishes to read and have cleared. The user writes a byte to one of these registers, with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register is updated with the latest information. When a 0 is written to a bit position, the read register is not updated and the previous value is held. A write to the status registers is immediately followed by a read of the same register. This write-read scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2156 with higher order languages. Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically network conditions such as loss-of-sync or all-ones detect. Event bits are typically markers such as the one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit. Some of the status registers have bits for both the detection of a condition and the clearance of the
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condition. For example, SR2 has a bit that is set when the device goes into a loss-of-sync state (SR2.0, a condition bit) and a bit that is set (SR2.4, an event bit) when the loss-of-sync condition clears (goes in sync). Some of the status register bits (condition bits) do not have a separate bit for the "condition clear" event but rather the status bit can produce interrupts on both edges, setting and clearing. These bits are marked as double interrupt bits. An interrupt is produced when the condition occurs and when it clears.
6.4
Information Registers
Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6 and INFO5 are not latched and it is not necessary to precede a read of these bits with a write.
6.5
Interrupt Information Registers
The interrupt information registers provide an indication of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read IIR1 and IIR2 to quickly identify which of the nine status registers are causing the interrupt.
Register Name: Register Description: Register Address: Bit # Name Default 7 SR8 0 IIR1 Interrupt Information Register 1 14h 6 SR7 0 5 SR6 0 4 SR5 0 3 SR4 0 2 SR3 0 1 SR2 0 0 SR1 0
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
IIR2 Interrupt Information Register 2 15h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 U_RSR 0 0 SR9 0
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7. CLOCK MAP
Figure 7-1 shows the clock map of the DS2156. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity.
Figure 7-1. Clock Map (TDM Mode)
MCLK TSYSCLK
MCLKS = 0 MCLKS = 1
PRE-SCALER 2.048 TO 1.544 SYNTHESIZER
LIC4.MPS0 LIC4.MPS1 LIC2.3
DJA = 1
8 x PLL
LOCAL LOOPBACK RCL = 1 JITTER ATTENUATOR SEE LIC1 REGISTER JAS = 0 AND DJA = 0 DJA = 0 REMOTE LOOPBACK FRAMER LOOPBACK PAYLOAD LOOPBACK (SEE NOTES)
8XCLK
LLB = 0
RXCLK
RCL = 0 LLB = 1
LTCA
FLB = 0
BPCLK SYNTH
BPCLK RCLK
RECEIVE FRAMER
TO LIU TXCLK
JAS = 0 OR DJA = 1
JAS = 1 OR DJA = 1 RLB = 1
FLB = 1
PLB = 1
LTCA
JAS = 1 AND DJA = 0 RLB = 0
TRANSMIT FORMATTER
PLB = 0
TCLK MUX
A B
C
TCLK
The TCLK MUX is dependent on the state of the TCSS0 and TCSS1 bits in the LIC1 register and the state of the TCLK pin.
TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLK pin (C) is always the source of transmit clock. Switch to the recovered clock (B) when the signal at the TCLK pin fails to transition after one channel time. Use the scaled signal (A) derived from MCLK as the transmit clock. The TCLK pin is ignored. Use the recovered clock (B) as the transmit clock. The TCLK pin is ignored.
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8. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS
The T1 framer portion of the DS2156 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2156 has been initialized, the control registers only need to be accessed when there is a change in the system configuration. There are two receive control registers (T1RCR1 and T1RCR2), two transmit control registers (T1TCR1 and T1TCR2), and a common control register (T1CCR1). Each of these registers is described in this section.
8.1
T1 Control Registers
T1RCR1 T1 Receive Control Register 1 03h 6 ARC 0 5 OOF1 0 4 OOF2 0 3 SYNCC 0 2 SYNCT 0 1 SYNCE 0 0 RESYNC 0
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
Bit 0/Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is initiated. Must be cleared and set again for a subsequent resync. Bit 1/Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 2/Sync Time (SYNCT) 0 = qualify 10 bits 1 = qualify 24 bits Bit 3/Sync Criteria (SYNCC) In D4 Framing Mode: 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode: 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Bits 4, 5/Out-of-Frame Select Bits (OOF2, OOF1) OOF2 0 0 1 1 OOF1 0 1 0 1 Out-Of-Frame Criteria 2/4 frame bits in error 2/5 frame bits in error 2/6 frame bits in error 2/6 frame bits in error
Bit 6/Auto Resync Criteria (ARC) 0 = resync on OOF or RCL event 1 = resync on OOF only Bit 7/Unused, must be set to 0 for proper operation 52 of 262
DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 T1RCR2 T1 Receive Control Register 2 04h 6 RFM 0 5 RB8ZS 0 4 RSLC96 0 3 RZSE 0 2 RZBTSI 0 1 RJC 0 0 RD4YM 0
Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM) 0 = 0s in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1/Receive Japanese CRC6 Enable (RJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Bit 2/Receive-Side ZBTSI Support Enable (RZBTSI). Allows ZBTSI information to be output on RLINK pin. 0 = ZBTSI disabled 1 = ZBTSI enabled Bit 3/Receive FDL Zero-Destuffer Enable (RZSE). Set this bit to 0 if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Section 22.5 for details. 0 = zero destuffer disabled 1 = zero destuffer enabled Bit 4/Receive SLC-96 Enable (RSLC96). Only set this bit to a 1 in D4/SLC-96 framing applications. See Section 22.6 for details. 0 = SLC-96 disabled 1 = SLC-96 enabled Bit 5/Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 6/Receive Frame Mode Select (RFM) 0 = D4 framing mode 1 = ESF framing mode Bit 7/Unused, must be set to 0 for proper operation
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Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0
T1TCR1 T1 Transmit Control Register 1 05h 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TFDLS 0 1 TBL 0 0 TYEL 0
Bit 0/Transmit Yellow Alarm (TYEL) 0 = do not transmit yellow alarm 1 = transmit yellow alarm Bit 1/Transmit Blue Alarm (TBL) 0 = transmit data normally 1 = transmit an unframed all-ones code at TPOS and TNEG Bit 2/TFDL Register Select (TFDLS) 0 = source FDL or Fs-bits from the internal TFDL register (legacy FDL support mode) 1 = source FDL or Fs-bits from the internal HDLC controller or the TLINK pin Bit 3/Global Bit 7 Stuffing (GB7S) 0 = allow the SSIEx registers to determine which channels containing all 0s are to be bit 7 stuffed 1 = force bit 7 stuffing in all 0-byte channels regardless of how the SSIEx registers are programmed Bit 4/Transmit Software Signaling Enable (TSSE). 0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still define which channels are to have B7 stuffing preformed. 1 = source signaling data as enabled by the SSIEx registers Bit 5/Transmit CRC Pass-Through (TCPT) 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time Bit 6/Transmit F-Bit Pass-Through (TFPT) 0 = F bits sourced internally 1 = F bits sampled at TSER Bit 7/Transmit Japanese CRC6 Enable (TJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TB8ZS 0 T1TCR2 T1 Transmit Control Register 2 06h 6 TSLC96 0 5 TZSE 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 TZBTSI 0 0 TB7ZS 0
Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS) 0 = no stuffing occurs 1 = bit 7 forced to a 1 in channels with all 0s Bit 1/Transmit-Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin. 0 = ZBTSI disabled 1 = ZBTSI enabled Bit 2/Transmit-Side D4 Yellow Alarm Select (TD4YM) 0 = 0s in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 Bit 3/F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization. Bit 4/F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Bit 5/Transmit FDL Zero-Stuffer Enable (TZSE). Set this bit to 0 if using the internal HDLC controller instead of the legacy support for the FDL. See Section 15 for details. 0 = zero stuffer disabled 1 = zero stuffer enabled Bit 6/Transmit SLC-96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern from the TFDL register. See Section 22.6 for details. 0 = SLC-96/Fs-bit insertion disabled 1 = SLC-96/Fs-bit insertion enabled Bit 7/Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 T1CCR1 T1 Common Control Register 1 07h 6 -- 0 5 -- 0 4 TRAI-CI 0 3 TAIS-CI 0 2 TFM 0 1 PDE 0 0 TLOOP 0
Bit 0/Transmit Loop-Code Enable (TLOOP). See Section 25 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2 Bit 1/Pulse Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for violations of these, which are required by ANSI T1.403: No more than 15 consecutive 0s and at least N 1s in each and every time window of 8 x (N + 1) bits, where N = 1 through 23. Violations for the transmit and receive data streams are reported in the INFO1.6 and INFO1.7 bits, respectively. When this bit is set to 1, the DS2156 forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to 0 since B8ZS encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer Bit 2/Transmit Frame Mode Select (TFM) 0 = D4 framing mode 1 = ESF framing mode Bit 3/Transmit AIS-CI Enable (TAIS-CI). Setting this bit and the TBL bit (T1TCR1.1) causes the AIS-CI code to be transmitted at TPOSO and TNEGO, as defined in ANSI T1.403. 0 = do not transmit the AIS-CI code 1 = transmit the AIS-CI code (T1TCR1.1 must also be set = 1) Bit 4/Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit position. 0 = do not transmit the ESF RAI-CI code 1 = transmit the ESF RAI-CI code Bits 5 to 7/Unused, must be set to 0 for proper operation
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8.2
T1 Transmit Transparency
The software signaling insertion-enable registers, SSIE1-SSIE4, can be used to select signaling insertion from the transmit signaling registers, TS1-TS12, on a per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced from the signaling registers for that channel. In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the channels. If a DS0 is programmed to be clear, no robbed-bit signaling is inserted nor does the channel have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 is overwritten by a 0 when a Yellow Alarm is transmitted. Also, the user has the option to globally override the SSIEx registers from determining which channels are to have bit 7 stuffing performed. If the T1TCR1.3 and T1TCR2.0 bits are set to 1, then all 24 T1 channels have bit 7 stuffing performed on them, regardless of how the SSIEx registers are programmed. In this manner, the SSIEx registers are only affecting the channels that are to have robbed-bit signaling inserted into them.
8.3
AIS-CI and RAI-CI Generation and Detection
The DS2156 can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes are compatible with and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These codes are defined in ANSI T1.403. The AIS-CI code (alarm indication signal-customer installation) is the same for both ESF and D4 operation. Setting the TAIS-CI bit in the T1CCR1 register and the TBL bit in the T1TCR1 register causes the DS2156 to transmit the AIS-CI code. The RAIS-CI status bit in the SR4 register indicates the reception of an AIS-CI signal. The RAI-CI (remote alarm indication-customer installation) code for T1 ESF operation is a special form of the ESF Yellow Alarm (an unscheduled message). Setting the RAIS-CI bit in the T1CCR1 register causes the DS2156 to transmit the RAI-CI code. The RAI-CI code causes a standard Yellow Alarm to be detected by the receiver. When the host processor detects a Yellow Alarm, it can then test the alarm for the RAI-CI state by checking the BOC detector for the RAI-CI flag. That flag is a 011111 code in the 6bit BOC message. The RAI-CI code for T1 D4 operation is a 10001011 flag in all 24 time slots. To transmit the RAI-CI code the host sets all 24 channels to idle with a 10001011 idle code. Since this code meets the requirements for a standard T1 D4 Yellow Alarm, the host can use the receive channel monitor function to detect the 100001011 code whenever a standard Yellow Alarm is detected.
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8.4
T1 Receive-Side Digital-Milliwatt Code Generation
Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registers represents a particular channel. If a bit is set to a 1, then the receive data in that channel is replaced with the digital-milliwatt code. If a bit is set to 0, no replacement occurs.
Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 T1RDMR1 T1 Receive Digital-Milliwatt Enable Register 1 0Ch 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels 1 to 8 (CH1 to CH8) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 T1RDMR2 T1 Receive Digital-Milliwatt Enable Register 2 0Dh 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels 9 to 16 (CH9 to CH16) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code
Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0
T1RDMR3 T1 Receive Digital-Milliwatt Enable Register 3 0Eh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels 17 to 24 (CH17 to CH24) 0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code
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Register Name: Register Description: Register Address: Bit # Name Default 7 RPDV 0
INFO1 Information Register 1 10h 6 TPDV 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0
Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. Bit 1/B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not by T1TCR2.7. Useful for automatically setting the line coding. Bit 2/Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in error. Bit 3/Sixteen Zero-Detect Event (16ZD). Set when a string of at least 16 consecutive 0s (regardless of the length of the string) have been received at RPOSI and RNEGI. Bit 4/Eight Zero-Detect Event (8ZD). Set when a string of at least eight consecutive 0s (regardless of the length of the string) have been received at RPOSI and RNEGI. Bit 5/Change-of-Frame Alignment Event (COFA). Set when the last resync resulted in a change-of-frame or multiframe alignment. Bit 6/Transmit Pulse-Density Violation Event (TPDV). Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 7/Receive Pulse-Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density.
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Table 8-A. T1 Alarm Criteria
ALARM Blue Alarm (AIS) (Note 1) Yellow Alarm (RAI) D4 Bit 2 Mode (T1RCR2.0 = 0) D4 12th F-Bit Mode (T1RCR2.0 = 1; this mode is also referred to as the "Japanese Yellow Alarm") ESF Mode SET CRITERIA When over a 3ms window, five or fewer 0s are received When bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences When the 12th framing bit is set to 1 for two consecutive occurrences CLEAR CRITERIA When over a 3ms window, six or more 0s are received When bit 2 of 256 consecutive channels is set to 0 for fewer than 254 occurrences When the 12th framing bit is set to 0 for two consecutive occurrences
When 16 consecutive patterns of 00FF appear in the FDL When 192 consecutive 0s are received
When 14 or fewer patterns of 00FF hex out of 16 possible appear in the FDL When 14 or more 1s out of 112 possible bit positions are received
Red Alarm (LRCL) (Also referred to as loss of signal)
Note 1: The definition of Blue Alarm (or AIS) is an unframed all-ones signal. Blue Alarm detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-1s signal. Blue Alarm criteria in the DS2156 has been set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit. Note 2: ANSI specifications use a different nomenclature than the DS2156 does. The following terms are equivalent: RBL = AIS RCL = LOS RLOS = LOF RYEL = RAI
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9. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS
The E1 framer portion of the DS2156 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2156 has been initialized, the control registers need only to be accessed when there is a change in the system configuration. There are two receive control registers (E1RCR1 and E1RCR2) and two transmit control registers (E1TCR1 and E1TCR2). There are also four status and information registers. Each of these eight registers is described in this section.
9.1
E1 Control Registers
E1RCR1 E1 Receive Control Register 1 33h 6 RSIGM 0 5 RHDB3 0 4 RG802 0 3 RCRC4 0 2 FRC 0 1 SYNCE 0 0 RESYNC 0
Register Name: Register Description: Register Address: Bit # Name Default 7 RSERC 0
Bit 0/Resync (RESYNC). When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync. Bit 1/Sync Enable (SYNCE) 0 = auto resync enabled 1 = auto resync disabled Bit 2/Frame Resync Criteria (FRC) 0 = resync if FAS received in error three consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times Bit 3/Receive CRC4 Enable (RCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 4/Receive G.802 Enable (RG802). See Section 16 for details. 0 = do not force RCHBLK high during bit 1 of time slot 26 1 = force RCHBLK high during bit 1 of time slot 26 Bit 5/Receive HDB3 Enable (RHDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 6/Receive Signaling Mode Select (RSIGM) 0 = CAS signaling mode 1 = CCS signaling mode Bit 7/RSER Control (RSERC) 0 = allow RSER to output data as received under all conditions 1 = force RSER to 1 under loss-of-frame alignment conditions
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Table 9-A. E1 Sync/Resync Criteria
FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA Three consecutive incorrect FAS received FAS FAS present in frame N and N + 2; FAS not present in frame N + 1 Two valid MF alignment words found within 8ms Valid MF alignment word found and previous time slot 16 contains code other than all 0s Alternate: (E1RCR1.2 = 1) The above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 codewords out of 1000 received in error Two consecutive MF alignment words received in error G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5.2 ITU SPEC.
CRC4 CAS
Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0
E1RCR2 E1 Receive Control Register 2 34h 6 Sa7S 0 5 Sa6S 0 4 Sa5S 0 3 Sa4S 0 2 -- 0 1 -- 0 0 RCLA 0
Bit 0/Receive Carrier-Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a receive carrier-loss condition for both the framer and LIU. 0 = RCL declared upon 255 consecutive 0s (125s) 1 = RCL declared upon 2048 consecutive 0s (1ms) Bits 1, 2/Unused, must be set to 0 for proper operation Bit 3/Sa4 Bit Select (Sa4S). Set to 1 to have RLCLK pulse at the Sa4 bit position; set to 0 to force RLCLK low during Sa4 bit position. See Section 34 for details. Bit 4/Sa5 Bit Select (Sa5S). Set to 1 to have RLCLK pulse at the Sa5 bit position; set to 0 to force RLCLK low during Sa5 bit position. See Section 34 for details. Bit 5/Sa6 Bit Select (Sa6S). Set to 1 to have RLCLK pulse at the Sa6 bit position; set to 0 to force RLCLK low during Sa6 bit position. See Section 34 for details. Bit 6/Sa7 Bit Select (Sa7S). Set to 1 to have RLCLK pulse at the Sa7 bit position; set to 0 to force RLCLK low during Sa7 bit position. See Section 34 for details. Bit 7/Sa8 Bit Select (Sa8S). Set to 1 to have RLCLK pulse at the Sa8 bit position; set to 0 to force RLCLK low during Sa8 bit position. See Section 34 for details.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TFPT 0 E1TCR1 E1 Transmit Control Register 1 35h 6 T16S 0 5 TUA1 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TG802 0 0 TCRC4 0
Bit 0/Transmit CRC4 Enable (TCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable (TG802). See Section 34 for details. 0 = do not force TCHBLK high during bit 1 of time slot 26 1 = force TCHBLK high during bit 1 of time slot 26 Bit 2/Transmit HDB3 Enable (THDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 3/Transmit Signaling All Ones (TSA1) 0 = normal operation 1 = force time slot 16 in every frame to all ones Bit 4/Transmit International Bit Select (TSiS) 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to 0) Bit 5/Transmit Unframed All Ones (TUA1) 0 = transmit data normally 1 = transmit an unframed all-ones code at TPOSO and TNEGO Bit 6/Transmit Time Slot 16 Data Select (T16S). See Section 15.2 for details. 0 = time slot 16 determined by the SSIEx registers and the THSCS function in the PCPR register 1 = source time slot 16 from TS1 to TS16 registers Bit 7/Transmit Time Slot 0 Pass-Through (TFPT) 0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/remote alarm sourced from TSER
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Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0
E1TCR2 E1 Transmit Control Register 2 36h 6 Sa7S 0 5 Sa6S 0 4 Sa5S 0 3 Sa4S 0 2 AEBE 0 1 AAIS 0 0 ARA 0
Bit 0/Automatic Remote Alarm Generation (ARA) 0 = disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) 0 = disabled 1 = enabled Bit 2/Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Bit 3/Sa4 Bit Select (Sa4S). Set to 1 to source the Sa4 bit from the TLINK pin; set to 0 to not source the Sa4 bit. See Section 34 for details. Bit 4/Sa5 Bit Select (Sa5S). Set to 1 to source the Sa5 bit from the TLINK pin; set to 0 to not source the Sa5 bit. See Section 34 for details. Bit 5/Sa6 Bit Select (Sa6S). Set to 1 to source the Sa6 bit from the TLINK pin; set to 0 to not source the Sa6 bit. See Section 34 for details. Bit 6/Sa7 Bit Select (Sa7S). Set to 1 to source the Sa7 bit from the TLINK pin; set to 0 to not source the Sa7 bit. See Section 34 for details. Bit 7/Sa8 Bit Select (Sa8S). Set to 1 to source the Sa8 bit from the TLINK pin; set to 0 to not source the Sa8 bit. See Section 34 for details.
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9.2
Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal). The framer forces either an AIS or remote alarm if any one or more of these conditions is present. When automatic RAI generation is enabled (E1TCR2.0 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss-of-receive-frame synchronization, AIS alarm (all ones) reception, loss-of-receive carrier (or signal), or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one or more of these conditions is present, then the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted if the DS2156 cannot find CRC4 multiframe synchronization within 400ms as per G.706. Note: It is an invalid state to have both automatic AIS generation and automatic remote alarm generation enabled at the same time.
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9.3
E1 Information Registers
INFO3 Information Register 3 12h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error. Bit 1/FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error. Bit 2/CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error. Register Name: Register Description: Register Address: Bit # Name Default 7 CSC5 0 INFO7 Information Register 7 (Real-Time, Non-Latched Register) 30h 6 CSC4 0 5 CSC3 0 4 CSC2 0 3 CSC0 0 2 FASSA 0 1 CASSA 0 0 CRC4SA 0
Bit 0/CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment word. This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write. Bit 1/CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word. This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write. Bit 2/FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level. This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write. Bits 3 to 7/CRC4 Sync Counter Bits (CSC0, CSC2 to CSC4). The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (E1RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action taken. The CRC4 sync counter rolls over. CSC0 is the LSB of the 6-bit counter. (Note: The bit next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.) These are read-only, non-latched, real-time bits. It is not necessary to precede the read of these bits with a write.
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Table 9-B. E1 Alarm Criteria
ALARM SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 255 or 2048 consecutive 0s received as determined by E1RCR2.0 Bit 3 of nonalign frame set to 1 for three consecutive occasions Fewer than three 0s in two frames (512 bits) Bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes Two out of three Sa7 bits are 0 CLEAR CRITERIA ITU SPECIFICATION
RLOS RCL RRA RUA1 RDMA V52LNK
At least 32 1s in 255-bit times are received Bit 3 of nonalign frame set to 0 for three consecutive occasions More than two 0s in two frames (512 bits)
G.775/G.962 O.162 2.1.4 O.162 1.6.1.2
G.965
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10.
COMMON CONTROL AND STATUS REGISTERS
CCR1 Common Control Register 1 70h 6 CRC4R 0 5 SIE 0 4 ODM 0 3 DICAI 0 2 TCSS1 0 1 TCSS0 0 0 RLOSF 0
Register Name: Register Description: Register Address: Bit # Name Default 7 MCLKS 0
Bit 0/Function of the RLOS/LOTC Output (RLOSF) 0 = receive loss of sync (RLOS) 1 = loss-of-transmit clock (LOTC) Bit 1/Transmit Clock Source Select Bit 0 (TCSS0) Bit 2/Transmit Clock Source Select Bit 0 (TCSS1) TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLK pin is always the source of transmit clock. Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after 1 channel time. Use the scaled signal present at MCLK as the transmit clock. The TCLK pin is ignored. Use the signal present at RCLK as the transmit clock. The TCLK pin is ignored.
Bit 3/Disable Idle Code Auto Increment (DICAI). Selects/deselects the auto-increment feature for the transmit and receive idle code array address register. See Section 16. 0 = addresses in IAAR register automatically increment on every read/write operation to the PCICR register 1 = addresses in IAAR register do not automatically increment Bit 4/Output Data Mode (ODM) 0 = pulses at TPOSO and TNEGO are one full TCLKO period wide 1 = pulses at TPOSO and TNEGO are one-half TCLKO period wide Bit 5/Signaling Integration Enable (SIE) 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for three multiframes in order for a change of state to be reported Bit 6/CRC-4 Recalculate (CRC4R) 0 = transmit CRC-4 generation and insertion operates in normal mode 1 = transmit CRC-4 generation operates according to G.706 intermediate path recalculation method Bit 7/MCLK Source (MCLKS). Selects the source of MCLK 0 = MCLK is source from the MCLK pin 1 = MCLK is source from the TSYSCLK pin
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 1 IDR Device Identification Register 0Fh 6 ID6 1 5 ID5 0 4 ID4 0 3 ID3 0 2 ID2 0 1 ID1 0 0 ID0 0
Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS2156 ID.
10.1 T1/E1 Status Registers
Register Name: Register Description: Register Address: Bit # Name Default 7 RYELC 0 SR2 Status Register 2 18h 6 RUA1C 0 5 FRCLC 0 4 RLOSC 0 3 RYEL 0 2 RUA1 0 1 FRCL 0 0 RLOS 0
Bit 0/Receive Loss-of-Sync Condition (RLOS). Set when the DS2156 is not synchronized to the received data stream. Bit 1/Framer Receive Carrier-Loss Condition (FRCL). Set when 255 (or 2048 if E1RCR2.0 = 1) E1 mode or 192 T1 mode consecutive 0s have been detected at RPOSI and RNEGI. Bit 2/Receive Unframed All-Ones (T1 Blue Alarm, E1 AIS) Condition (RUA1). Set when an unframed all 1s code is received at RPOSI and RNEGI. Bit 3/Receive Yellow Alarm Condition (RYEL) (T1 Only). Set when a Yellow Alarm is received at RPOSI and RNEGI. Bit 4/Receive Loss-of-Sync Clear Event (RLOSC). Set when the framer achieves synchronization; remains set until read. Bit 5/Framer Receive Carrier-Loss Clear Event (FRCLC). Set when the carrier loss condition at RPOSI and RNEGI is no longer detected. Bit 6/Receive Unframed All-Ones Clear Event (RUA1C). Set when the unframed all 1s condition is no longer detected. Bit 7/Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the receive Yellow Alarm condition is no longer detected.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RYELC 0 IMR2 Interrupt Mask Register 2 19h 6 RUA1C 0 5 FRCLC 0 4 RLOSC 0 3 RYEL 0 2 RUA1 0 1 FRCL 0 0 RLOS 0
Bit 0/Receive Loss-of-Sync Condition (RLOS) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 1/Framer Receive Carrier Loss Condition (FRCL) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 2/Receive Unframed All-Ones (Blue Alarm) Condition (RUA1) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 3/Receive Yellow Alarm Condition (RYEL) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 4/Receive Loss-of-Sync Clear Event (RLOSC) 0 = interrupt masked 1 = interrupt enabled Bit 5/Framer Receive Carrier Loss Condition Clear (FRCLC) 0 = interrupt masked 1 = interrupt enabled Bit 6/Receive Unframed All-Ones Condition Clear Event (RUA1C) 0 = interrupt masked 1 = interrupt enabled Bit 7/Receive Yellow Alarm Clear Event (RYELC) 0 = interrupt masked 1 = interrupt enabled
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 SR3 Status Register 3 1Ah 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0
Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. This is a double interrupt bit. See Section 6.3. Bit 1/Receive Distant MF Alarm Condition (RDMA) (E1 Only). Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is a double interrupt bit. See Section 6.3. Bit 2/V5.2 Link Detected Condition (V52LNK) (E1 Only). Set on detection of a V5.2 link identification signal (G.965). This is a double interrupt bit. See Section 6.3. Bit 3/Loss-of-Receive Clock Condition (LORC). Set when the RCLKI pin has not transitioned for one channel time. This is a double interrupt bit. See Section 6.3. Bit 4/Loss-of-Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for one channel time. Forces the LOTC pin high if enabled by CCR1.0. This is a double interrupt bit. See Section 6.3. Bit 5/Loop-Up Code Detected Condition (LUP) (T1 Only). Set when the loop-up code as defined in the RUPCD1/2 register is being received. See Section 25 for details. This is a double interrupt bit. See Section 6.3. Bit 6/Loop-Down Code Detected Condition (LDN) (T1 Only). Set when the loop down code as defined in the RDNCD1/2 register is being received. See Section 25 for details. This is a double interrupt bit. See Section 6.3. Bit 7/Spare Code Detected Condition (LSPARE) (T1 Only). Set when the spare code as defined in the RSCD1/2 registers is being received. See Section 25 for details. This is a double interrupt bit. See Section 6.3.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 IMR3 Interrupt Mask Register 3 1Bh 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0
Bit 0/Receive Remote Alarm Condition (RRA) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 1/Receive Distant MF Alarm Condition (RDMA) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 2/V5.2 Link Detected Condition (V52LNK) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 3/Loss-of-Receive Clock Condition (LORC) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 4/Loss-of-Transmit Clock Condition (LOTC) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 5/Loop-Up Code-Detected Condition (LUP) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 6/Loop-Down Code-Detected Condition (LDN) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 7/Spare Code Detected Condition (LSPARE) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 SR4 Status Register 4 1Ch 6 RSAO 0 5 RSAZ 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0
Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250s at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1/Receive CRC4 Multiframe Event (RCMF) (E1 Only). Set on CRC4 multiframe boundaries; continues to set every 2ms on an arbitrary boundary if CRC4 is disabled. Bit 2/Receive Multiframe Event (RMF) E1 Mode: Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available. T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. Bit 3/Transmit Align Frame Event (TAF) (E1 Only). Set every 250s at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Bit 4/Transmit Multiframe Event (TMF) E1 Mode: Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. Bit 5/Receive Signaling All-Zeros Event (RSAZ) (E1 Only). Set when over a full MF, time slot 16 contains all 0s. Bit 6/Receive Signaling All-Ones Event (RSAO) (E1 Only). Set when the contents of time slot 16 contains fewer than three 0s over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 7/Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI T1.403.
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Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0
IMR4 Interrupt Mask Register 4 1Dh 6 RSAO 0 5 RSAZ 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0
Bit 0/Receive Align Frame Event (RAF) 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe Event (RCMF) 0 = interrupt masked 1 = interrupt enabled Bit 2/Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled Bit 3/Transmit Align Frame Event (TAF) 0 = interrupt masked 1 = interrupt enabled Bit 4/Transmit Multiframe Event (TMF) 0 = interrupt masked 1 = interrupt enabled Bit 5/Receive Signaling All-Zeros Event (RSAZ) 0 = interrupt masked 1 = interrupt enabled Bit 6/Receive Signaling All-Ones Event (RSAO) 0 = interrupt masked 1 = interrupt enabled Bit 7/Receive AIS-CI Event (RAIS-CI) 0 = interrupt masked 1 = interrupt enabled
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11.
I/O PIN CONFIGURATION OPTIONS
IOCR1 I/O Configuration Register 1 01h 6 RSMS2 0 5 RSMS1 0 4 RSIO 0 3 TSDW 0 2 TSM 0 1 TSIO 0 0 ODF 0
Register Name: Register Description: Register Address: Bit # Name Default 7 RSMS 0
Bit 0/Output Data Format (ODF) 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0 Bit 1/TSYNC I/O Select (TSIO) 0 = TSYNC is an input 1 = TSYNC is an output Bit 2/TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin. See the timing diagrams in Section 34. 0 = frame mode 1 = multiframe mode Bit 3/TSYNC Double-Wide (TSDW). (Note: This bit must be set to 0 when IOCR1.2 = 1 or when IOCR1.1 = 0.) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames Bit 4/RSYNC I/O Select (RSIO). (Note: This bit must be set to 0 when ESCR.0 = 0.) 0 = RSYNC is an output 1 = RSYNC is an input (only valid if elastic store enabled) Bit 5/RSYNC Mode Select 1(RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input mode (elastic store must be enabled), multiframe mode is only useful when receive signaling reinsertion is enabled. See the timing diagrams in Section 34. 0 = frame mode 1 = multiframe mode Bit 6/RSYNC Mode Select 2 (RSMS2) T1 Mode: RSYNC pin must be programmed in the output frame mode (IOCR1.5 = 0, IOCR1.4 = 0). 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames E1 Mode: RSYNC pin must be programmed in the output multiframe mode (IOCR1.5 = 1, IOCR1.4 = 0). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries Bit 7/RSYNC Multiframe Skip Control (RSMS). Useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses (IOCR1.5 = 1 and IOCR1.4 = 0). 0 = RSYNC outputs a pulse at every multiframe 1 = RSYNC outputs a pulse at every other multiframe
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Register Name: Register Description: Register Address: Bit # Name Default 7 RCLKINV 0
IOCR2 I/O Configuration Register 2 02h 6 TCLKINV 0 5 RSYNCINV 0 4 TSYNCINV 0 3 TSSYNCINV 0 2 H100EN 0 1 TSCLKM 0 0 RSCLKM 0
Bit 0/RSYSCLK Mode Select (RSCLKM) 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled (See Section 28 for details on IBO function.) Bit 1/TSYSCLK Mode Select (TSCLKM) 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.048MHz or IBO enabled (See Section 28 for details on IBO function.) Bit 2/H.100 SYNC Mode (H100EN) 0 = normal operation 1 = SYNC shift Bit 3/TSSYNC Invert (TSSYNCINV) 0 = no inversion 1 = invert Bit 4/TSYNC Invert (TSYNCINV) 0 = no inversion 1 = invert Bit 5/RSYNC Invert (RSYNCINV) 0 = no inversion 1 = invert Bit 6/TCLK Invert (TCLKINV) 0 = no inversion 1 = invert Bit 7/RCLK Invert (RCLKINV) 0 = no inversion 1 = invert
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12.
LOOPBACK CONFIGURATION
LBCR Loopback Control Register 4Ah 6 -- 0 5 -- 0 4 LIUC 0 3 LLB 0 2 RLB 0 1 PLB 0 0 FLB 0
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
Bit 0/Framer Loopback (FLB). This loopback is useful in testing and debugging applications. In FLB, the DS2156 loops data from the transmit side back to the receive side. When FLB is enabled, the following occurs:
1) T1 Mode: An unframed all-ones code is transmitted at TPOSO and TNEGO.
E1 Mode: Normal data is transmitted at TPOSO and TNEGO.
2) Data at RPOSI and RNEGI is ignored. 3) All receive-side signals take on timing synchronous with TCLK instead of RCLKI.
Please note that it is not acceptable to have RCLK connected to TCLK during this loopback because this causes an unstable condition. 0 = loopback disabled 1 = loopback enabled Bit 1/Payload Loopback (PLB). When PLB is enabled, the following occurs:
1) 2) 3) 4)
Data is transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK. All the receive side signals continue to operate normally. Data at the TSER, TDATA, and TSIG pins is ignored. The TLCLK signal becomes synchronous with RCLK instead of TCLK. 0 = loopback disabled 1 = loopback enabled T1 Mode. Normally, this loopback is only enabled when ESF framing is being performed but can also be enabled in D4 framing applications. In a PLB situation, the DS2156 loops the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back; they are reinserted by the DS2156. E1 Mode. In a PLB situation, the DS2156 loops the 248 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The transmit section modifies the payload as if it was input at TSER. The FAS word; Si, Sa, and E bits; and CRC4 are not looped back; they are reinserted by the DS2156.
Bit 2/Remote Loopback (RLB). In this loopback, data input by the RPOSI and RNEGI pins is transmitted back to the TPOSO and TNEGO pins. Data continues to pass through the receive-side framer of the DS2156 as it would normally. Data from the transmit-side formatter is ignored. See Figure 2-1 for more details. 0 = loopback disabled 1 = loopback enabled
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DS2156 Bit 3/Local Loopback (LLB). In this loopback, data continues to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING are replaced with the data being transmitted. Data in this loopback passes through the jitter attenuator. See Figure 2-2 for more details. 0 = loopback disabled 1 = loopback enabled Bit 4/Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the LIUC pin is connected high, the LIUC bit has control. When the LIUC pin is connected low, the framer and LIU are separated and the LIUC bit has no effect 0 = if LIUC pin connected high, LIU internally connected to framer block and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins 1 = if LIUC pin connected high, disconnect LIU from framer block and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins LIUC Pin 0 0 1 1 LIUC Bit 0 1 0 1 Condition LIU and framer separated LIU and framer separated LIU and framer connected LIU and framer separated
Bits 5 to 7/Unused, must be set to 0 for proper operation
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12.1 Per-Channel Loopback
The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this is to connect RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. Each of the bit positions in the per-channel loopback registers (PCLR1/PCLR2/PCLR3/PCLR4) represents a DS0 channel in the outgoing frame. When these bits are set to a 1, data from the corresponding receive channel replaces the data on TSER for that channel.
Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 PCLR1 Per-Channel Loopback Enable Register 1 4Bh 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 1 to 8 (CH1 to CH8) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 PCLR2 Per-Channel Loopback Enable Register 2 4Ch 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 9 to 16 (CH9 to CH16) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 PCLR3 Per-Channel Loopback Enable Register 3 4Dh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 PCLR4 Per-Channel Loopback Enable Register 4 4Eh 6 CH31 0 5 CH30 0 4 CH29 0 3 CH28 0 2 CH27 0 1 CH26 0 0 CH25 0
Bits 0 to 7/Per-Channel Loopback Enable for Channels 25 to 32 (CH25 to CH32) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel
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13.
ERROR COUNT REGISTERS
The DS2156 contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters saturate at their respective maximum counts, and they do not roll over. Note: Only the linecode violation count register has the potential to overflow, but the bit error would have to exceed 10E-2 before this would occur.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 ERCNT Error-Counter Configuration Register 41h 6 MECU 0 5 ECUS 0 4 EAMS 0 3 VCRFS 0 2 FSBE 0 1 MOSCRF 0 0 LCVCRF 0
Bit 0/T1 Line-Code Violation Count Register Function Select (LCVCRF) 0 = do not count excessive 0s 1 = count excessive 0s Bit 1/Multiframe Out-of-Sync Count Register Function Select (MOSCRF) 0 = count errors in the framing bit position 1 = count the number of multiframes out-of-sync Bit 2/PCVCR Fs-Bit Error-Report Enable (FSBE) 0 = do not report bit errors in Fs-bit position; only Ft-bit position 1 = report bit errors in Fs-bit position as well as Ft-bit position Bit 3/E1 Line-Code Violation Count Register Function Select (VCRFS) 0 = count bipolar violations (BPVs) 1 = count code violations (CVs) Bit 4/Error-Accumulation Mode Select (EAMS) 0 = ERCNT.5 determines accumulation time 1 = ERCNT.6 determines accumulation time Bit 5/Error-Counter Update Select (ECUS) T1 Mode: 0 = update error counters once a second 1 = update error counters every 42ms (333 frames) E1 Mode: 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) Bit 6/Manual Error-Counter Update (MECU). When enabled by ERCNT.4, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error-counter registers with the latest counts and reset the counters. The user must wait a minimum of 1.5 RCLK clock periods before reading the error count registers to allow for proper update. Bit 7/Unused, must be set to 0 for proper operation 81 of 262
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13.1 Line-Code Violation Count Register (LCVCR)
13.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not disabled during receive loss-of-synchronization (RLOS = 1) conditions. Table 13-A shows what the LCVCRs count.
Table 13-A. T1 Line Code Violation Counting Options
COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (T1RCR2.5) No No Yes Yes COUNTED IN THE LCVCRs BPVs BPVs + 16 consecutive 0s BPVs (B8ZS codewords not counted) BPVs + 8 consecutive 0s
13.1.2 E1 Operation Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as BPVs. If ERCNT.3 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss-of-sync conditions. The counter saturates at 65,535 and does not roll over. The bit-error rate on an E1 line would have to be greater than 10-2 before the VCR would saturate (Table 13-B).
Table 13-B. E1 Line-Code Violation Counting Options
E1 CODE VIOLATION SELECT (ERCNT.3) 0 1 COUNTED IN THE LCVCRs BPVs CVs
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 LCVCR1 Line-Code Violation Count Register 1 42h 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0
Bits 0 to 7/Line-Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count. Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC7 0 LCVCR2 Line-Code Violation Count Register 2 43h 6 LCVC6 0 5 LCVC5 0 4 LCVC4 0 3 LCVC3 0 2 LCVC2 0 1 LCVC1 0 0 LCVC0 0
Bits 0 to 7/Line-Code Violation Counter Bits 0 to 7 (LCVC0 to LCVC7). LCV0 is the LSB of the 16-bit code violation count.
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13.2 Path Code Violation Count Register (PCVCR)
13.2.1 T1 Operation The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position. Through the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR is disabled during receive loss-of-synchronization (RLOS = 1) conditions. Table 13-C shows what errors the PCVCR counts.
Table 13-C. T1 Path Code Violation Counting Arrangements
FRAMING MODE D4 D4 ESF COUNT Fs ERRORS? No Yes Don't Care COUNTED IN THE PCVCRs Errors in the Ft pattern Errors in both the Ft and Fs patterns Errors in the CRC6 codewords
13.2.2 E1 Operation The path code violation-count register records CRC4 errors. Since the maximum CRC4 count in a onesecond period is 1000, this counter cannot saturate. The counter is disabled during loss-of-sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. Path code violation-count register 1 (PCVCR1) is the most significant word and PCVCR2 is the least significant word of a 16-bit counter that records path violations (PVs).
Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC15 0 PCVCR1 Path Code Violation Count Register 1 44h 6 PCVC14 0 5 PCVC13 0 4 PCVC12 0 3 PCVC11 0 2 PCVC10 0 1 PCVC9 0 0 PCVC8 0
Bits 0 to 7/Path Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit path code violation count. Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC7 0 PCVCR2 Path Code Violation Count Register 2 45h 6 PCVC6 0 5 PCVC5 0 4 PCVC4 0 3 PCVC3 0 2 PCVC2 0 1 PCVC1 0 0 PCVC0 0
Bits 0 to 7/Path Code Violation Counter Bits 0 to 7 (PCVC0 to PCVC7). PCVC0 is the LSB of the 16-bit path code violation count.
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13.3 Frames Out-of-Sync Count Register (FOSCR)
13.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss-of-synchronization (RLOS = 1) conditions. The FOSCR has an alternate operating mode whereby it counts either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is disabled during receive loss-of-synchronization (RLOS = 1) conditions. Table 13-D shows what the FOSCR is capable of counting.
Table 13-D. T1 Frames Out-of-Sync Counting Arrangements
FRAMING MODE (T1RCR1.3) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (ERCNT.1) MOS F-Bit MOS F-Bit COUNTED IN THE FOSCRs Number of multiframes out-of-sync Errors in the Ft pattern Number of multiframes out-of-sync Errors in the FPS pattern
13.3.2 E1 Operation The FOSCR counts word errors in the FAS in time slot 0. This counter is disabled when RLOS is high. FAS errors are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot saturate. The frames out-of-sync count register 1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16-bit counter that records frames out-of-sync.
Register Name: Register Description: Register Address: Bit # Name Default 7 FOS15 0 FOSCR1 Frames Out-of-Sync Count Register 1 46h 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0
Bits 0 to 7/Frames Out-of-Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out-of-sync count. Register Name: Register Description: Register Address: Bit # Name Default 7 FOS7 0 FOSCR2 Frames Out-of-Sync Count Register 2 47h 6 FOS6 0 5 FOS5 0 4 FOS4 0 3 FOS3 0 2 FOS2 0 1 FOS1 0 0 FOS0 0
Bits 0 to 7/Frames Out-of-Sync Counter Bits 0 to 7 (FOS0 to FOS7). FOS0 is the LSB of the 16-bit frames outof-sync count. 85 of 262
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13.4 E-Bit Counter (EBCR)
This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a onesecond period is 1000, this counter cannot saturate. The counter is disabled during loss-of-sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level.
Register Name: Register Description: Register Address: Bit # Name Default 7 EB15 0 EBCR1 E-Bit Count Register 1 48h 6 EB14 0 5 EB13 0 4 EB12 0 3 EB11 0 2 EB10 0 1 EB9 0 0 EB8 0
Bits 0 to 7/E-Bit Counter Bits 8 to 15 (EB8 to EB15). EB15 is the MSB of the 16-bit E-bit count. Register Name: Register Description: Register Address: Bit # Name Default 7 EB7 0 EBCR2 E-Bit Count Register 2 49h 6 EB6 0 5 EB5 0 4 EB4 0 3 EB3 0 2 EB2 0 1 EB1 0 0 EB0 0
Bits 0 to 7/E-Bit Counter Bits 0 to 7 (EB0 to EB7). EB0 is the LSB of the 16-bit E-bit count.
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14.
DS0 MONITORING FUNCTION
The DS2156 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits appear in the transmit DS0 monitor (TDS0M) register. The DS0 channel pointed to by the RCM0 to RCM4 bits appear in the receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
TDS0SEL Transmit Channel Monitor Select 74h 6 -- 0 5 -- 0 4 TCM4 0 3 TCM3 0 2 TCM2 0 1 TCM1 0 0 TCM0 0
Bits 0 to 4/Transmit Channel Monitor Bits (TCM0 to TCM4). TCM0 is the LSB of a 5-bit channel select that determines which transmit channel data appear in the TDS0M register. Bits 5 to 7/Unused, must be set to 0 for proper operation
Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0
TDS0M Transmit DS0 Monitor Register 75h 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0
Bits 0 to 7/Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the transmit channel monitor select register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 RDS0SEL Receive Channel Monitor Select 76h 6 -- 0 5 -- 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0
Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data appear in the RDS0M register. Bits 5 to 7/Unused, must be set to 0 for proper operation Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 RDS0M Receive DS0 Monitor Register 77h 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0
Bits 0 to 7/Receive DS0 Channel Bits (B1 to B8). Receive channel data that has been selected by the receive channel monitor select register. B8 is the LSB of the DS0 channel (last bit to be received).
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15.
SIGNALING OPERATION
There are two methods to access receive signaling data and provide transmit signaling data, processorbased (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1-RS16 and TS1-TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously.
15.1 Receive Signaling Figure 15-1. Simplified Diagram of Receive Signaling Path
PER-CHANNEL CONTROL T1/E1 DATA STREAM
SIGNALING EXTRACTION ALL-ONES
RSER
RECEIVE SIGNALING REGISTERS CHANGE-OF-STATE INDICATION REGISTERS
REINSERTION CONTROL SIGNALING BUFFERS
RSYNC RSIG
15.1.1 Processor-Based Signaling The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and copied into the receive signaling registers, RS1-RS16. In T1 mode, only RS1-RS12 are used. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. 15.1.1.1 Change-of-State To avoid constant monitoring of the receive signaling registers, the DS2156 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1-RSCSE4 for E1 and RSCSE1-RSCSE3 for T1 are used to select which channels can cause a change-of-state indication. The change-of-state is indicated in status register 5 (SR1.5). If signaling integration (CCR1.5) is enabled, then the new signaling state must be constant for three multiframes before a change-of-state is indicated. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the IMR1.5 bit. The signaling integration mode is global and cannot be enabled on a channel-by-channel basis. The user can identity which channels have undergone a signaling change-of-state by reading the RSINFO1-RSINFO4 registers. The information from these registers inform the user which RSx register to read for the new signaling data. All changes are indicated in the RSINFO1-RSINFO4 registers regardless of the RSCSE1-RSCSE4 registers.
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15.1.2 Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER. The signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each channel. The RSIG data is updated once a multiframe (1.5ms) unless a freeze is in effect. See the timing diagrams in Section 34 for some examples. 15.1.2.1 Receive Signaling Reinsertion at RSER In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data is reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream, the original signaling data and the realigned data. This is of little consequence in voice channels. Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. In this mode, the elastic store must be enabled; however, the backplane clock can be either 1.544MHz or 2.048MHz. Signaling reinsertion can be enabled on a per-channel basis by setting the RSRCS bit high in the PCPR register. The channels that will have signaling reinserted are selected by writing to the PCDR1-PCDR3 registers for T1 mode and PCDR1-PCDR4 registers for E1 mode. In E1 mode, the user generally selects all channels or none for reinsertion. In E1 mode, signaling reinsertion on all channels can be enabled with a single bit, SIGCR.7 (GRSRE). This bit allows the user to reinsert all signaling channels without having to program all channels through the per-channel function. 15.1.2.2 Force Receive Signaling All Ones In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to a 1 by using the per-channel register (Section 5). The user sets the BTCS bit in the PCPR register. The channels that will be forced to 1 are selected by writing to the PCDR1-PCDR3 registers. 15.1.2.3 Receive Signaling Freeze The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit (SIGCR.4) should be set high. The user can force a freeze by setting the RFF control bit (SIGCR.3) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receive signaling reinsertion is enabled). When freezing is enabled (RFE = 1), the signaling data is held in the last-known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data is held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before updating with new signaling data.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 GRSRE 0 SIGCR Signaling Control Register 40h 6 -- 0 5 -- 0 4 RFE 0 3 RFF 0 2 RCCS 0 1 TCCS 0 0 FRSAO 0
Bit 0/Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and RSER pin to all ones. This bit has no effect in E1 mode. 0 = normal signaling data at RSIG and RSER 1 = force signaling data at RSIG and RSER to all ones Bit 1/Transmit Time Slot Control for CAS Signaling (TCCS). Controls the order that signaling is transmitted from the transmit signaling registers. This bit should be set = 0 in T1 mode. 0 = signaling data is CAS format 1 = signaling data is CCS format Bit 2/Receive Time Slot Control for CAS Signaling (RCCS). Controls the order that signaling is placed into the receive signaling registers. This bit should be set = 0 in T1 mode. 0 = signaling data is CAS format 1 = signaling data is CCS format Bit 3/Receive Force Freeze (RFF). Freezes receive-side signaling at RSIG (and RSER if receive signaling reinsertion is enabled); overrides receive freeze enable (RFE). See Section 15.1.2.3 for details. 0 = do not force a freeze event 1 = force a freeze event Bit 4/Receive Freeze Enable (RFE). See Section 15.1.2.3 for details. 0 = no freezing of receive signaling data occurs 1 = allow freezing of receive signaling data at RSIG (and RSER if receive signaling reinsertion is enabled) Bits 5, 6/Unused, must be set to 0 for proper operation Bit 7/Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling channels without programming all channels through the per-channel function. 0 = do not reinsert all signaling 1 = reinsert all signaling
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DS2156 Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A RS1 to RS12 Receive Signaling Registers (T1 Mode, ESF Format) 60h to 6Bh CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH2-D CH4-D CH6-D CH8-D CH10-D CH12-D CH14-D CH16-D CH18-D CH20-D CH22-D CH24-D CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B CH1-C CH3-C CH5-C CH7-C CH9-C CH11-C CH13-C CH15-C CH17-C CH19-C CH21-C CH23-C (LSB) CH1-D CH3-D CH5-D CH7-D CH9-D CH11-D CH13-D CH15-D CH17-D CH19-D CH21-D CH23-D RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12
CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B
Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A
RS1 to RS12 Receive Signaling Registers (T1 Mode, D4 Format) 60h to 6Bh CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B (LSB) CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12
CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B
CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A
CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B
CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A
Note: In D4 format, TS1-TS12 contain signaling data for two frames. Bold type indicates data for second frame.
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DS2156 Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A RS1 to RS16 Receive Signaling Registers (E1 Mode, CAS Format) 60h to 6Fh 0 CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH26-C CH28-C CH30-C 0 CH2-D CH4-D CH6-D CH8-D CH10-D CH12-D CH14-D CH16-D CH18-D CH20-D CH22-D CH24-D CH26-D CH28-D CH30-D X CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A CH25-A CH27-A CH29-A Y CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B CH25-B CH27-B CH29-B X CH1-C CH3-C CH5-C CH7-C CH9-C CH11-C CH13-C CH15-C CH17-C CH19-C CH21-C CH23-C CH25-C CH27-C CH29-C (LSB) X CH1-D CH3-D CH5-D CH7-D CH9-D CH11-D CH13-D CH15-D CH17-D CH19-D CH21-D CH23-D CH25-D CH27-D CH29-D RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16
0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B
Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121
RS1 to RS16 Receive Signaling Registers (E1 Mode, CCS Format) 60h to 6Fh 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 5 13 21 29 37 45 53 61 69 77 85 93 101 109 117 125 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 (LSB) 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16
2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122
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DS2156 Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive Signaling Change-of-State Interrupt Enable 3Ch, 3Dh, 3Eh, 3Fh CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RSCSE1 RSCSE2 RSCSE3 RSCSE4
CH7 CH15 CH23
Setting any of the CH1-CH30 bits in the RSCSE1-RSCSE4 registers causes an interrupt when that channel's signaling data changes state.
Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24
RSINFO1, RSINFO2, RSINFO3, RSINFO4 Receive Signaling Change-of-State Information 38h, 39h, 3Ah, 3Bh CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RSINFO1 RSINFO2 RSINFO3 RSINFO4
CH7 CH15 CH23
When a channel's signaling data changes state, the respective bit in registers RSINFO1-4 is set. An interrupt is generated if the channel was also enabled as an interrupt source by setting the appropriate bit in RSCSE1-4. The bit remains set until read.
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15.2 Transmit Signaling Figure 15-2. Simplified Diagram of Transmit Signaling Path
TRANSMIT SIGNALING REGISTERS 1 0 T1/E1 DATA STREAM 0 1 B7 T1TCR1.4 PER-CHANNEL CONTROL SSIE1 - SSIE4 ONLY APPLIES TO T1 MODE PER-CHANNEL CONTROL PCPR.3 1 SIGNALING BUFFERS TSIG 0 TSER
15.2.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1-TS16) by the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can employ the transmit multiframe interrupt in status register 4 (SR4.4) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change-of-state for that register. Each transmit signaling register contains the robbed-bit signaling (T1) or TS16 CAS signaling (E1) for two time slots that are inserted into the outgoing stream, if enabled to do so through T1TCR1.4 (T1 mode) or E1TCR1.6 (E1 mode). In T1 mode, only TS1-TS12 are used. Signaling data can be sourced from the TS registers on a per-channel basis by using the software signaling insertion enable registers, SSIE1-SSIE4. 15.2.1.1 T1 Mode In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1-TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. In D4 mode, two multiframes of signaling data can be loaded into TS1-TS12. The framer loads the contents of TS1-TS12 into the outgoing shift register every other D4 multiframe. In D4 mode, the host should load new contents into TS1-TS12 on every other multiframe boundary and no later than 120s after the boundary.
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15.2.1.2 E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In "Channel" numbering, TS0-TS31 are labeled channels 1 through 32. In "Phone Channel" numbering, TS1-TS15 are labeled channel 1 through channel 15 and TS17-TS31 are labeled channel 15 through channel 30.
Table 15-A. Time Slot Numbering Schemes
0 1 2 3 4 5 6 7 8 9 10 11 1213 14 1516 17 1819 20 2122 23 2425 26 27 28 29 30 31 TS Channel 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 1617 18 1920 21 2223 24 2526 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 2021 22 2324 25 26 27 28 29 30 Phone Channel
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DS2156 Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A TS1 to TS16 Transmit Signaling Registers (E1 Mode, CAS Format) 50h to 5Fh 0 CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH26-C CH28-C CH30-C 0 CH2-D CH4-D CH6-D CH8-D CH10-D CH12-D CH14-D CH16-D CH18-D CH20-D CH22-D CH24-D CH26-D CH28-D CH30-D X CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A CH25-A CH27-A CH29-A Y CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B CH25-B CH27-B CH29-B X CH1-C CH3-C CH5-C CH7-C CH9-C CH11-C CH13-C CH15-C CH17-C CH19-C CH21-C CH23-C CH25-C CH27-C CH29-C (LSB) X CH1-D CH3-D CH5-D CH7-D CH9-D CH11-D CH13-D CH15-D CH17-D CH19-D CH21-D CH23-D CH25-D CH27-D CH29-D TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B
Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121
TS1 to TS16 Transmit Signaling Registers (E1 Mode, CCS Format) 50h to 5Fh 3 11 19 27 35 43 51 59 67 75 83 91 99 107 115 123 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 5 13 21 29 37 45 53 61 69 77 85 93 101 109 117 125 6 14 22 30 38 46 54 62 70 78 86 94 102 110 118 126 7 15 23 31 39 47 55 63 71 79 87 95 103 111 119 127 (LSB) 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122
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Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A
TS1 to TS12 Transmit Signaling Registers (T1 Mode, ESF Format) 50h to 5Bh CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH2-D CH4-D CH6-D CH8-D CH10-D CH12-D CH14-D CH16-D CH18-D CH20-D CH22-D CH24-D CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B CH1-C CH3-C CH5-C CH7-C CH9-C CH11-C CH13-C CH15-C CH17-C CH19-C CH21-C CH23-C (LSB) CH1-D CH3-D CH5-D CH7-D CH9-D CH11-D CH13-D CH15-D CH17-D CH19-D CH21-D CH23-D TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12
CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B
Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A
TS1 to TS12 Transmit Signaling Registers (T1 Mode, D4 Format) 50h to 5Bh CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B (LSB) CH1-B CH3-B CH5-B CH7-B CH9-B CH11-B CH13-B CH15-B CH17-B CH19-B CH21-B CH23-B TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12
CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B
CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A
CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B
CH1-A CH3-A CH5-A CH7-A CH9-A CH11-A CH13-A CH15-A CH17-A CH19-A CH21-A CH23-A
Note: In D4 format, TS1-TS12 contain signaling data for two frames. Bold type indicates data for second frame.
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15.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data.
Register Name: Register Description: Register Address: Bit # Name Default 7 CH7 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH6 0 5 CH5 0 4 CH4 0 3 CH3 0 2 CH2 0 1 CH1 0 0 UCAW 0
Bit 0/Upper CAS Align/Alarm Word (UCAW). Selects the upper CAS align/alarm pattern (0000) to be sourced from the upper 4 bits of the TS1 register. 0 = do not source the upper CAS align/alarm pattern from the TS1 register 1 = source the upper CAS align/alarm pattern from the TS1 register Bits 1 to 7/Software Signaling-Insertion Enable for Channels 1 to 7 (CH1 to CH7). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel Register Name: Register Description: Register Address: Bit # Name Default 7 CH15 0 SSIE2 Software Signaling Insertion Enable 2 09h 6 CH14 0 5 CH13 0 4 CH12 0 3 CH11 0 2 CH10 0 1 CH9 0 0 CH8 0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 8 to 15 (CH8 to CH15). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 CH22 0 SSIE3 Software Signaling Insertion Enable 3 0Ah 6 CH21 0 5 CH20 0 4 CH19 0 3 CH18 0 2 CH17 0 1 CH16 0 0 LCAW 0
Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from the lower 4 bits of the TS1 register. 0 = do not source the lower CAS align/alarm bits from the TS1 register 1 = source the lower CAS alarm align/bits from the TS1 register Bits 1 to 7/Software Signaling Insertion Enable for LCAW and Channels 16 to 22 (CH16 to CH22). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel
Register Name: Register Description: Register Address: Bit # Name Default 7 CH30 0
SSIE4 Software Signaling Insertion Enable 4 0Bh 6 CH29 0 5 CH28 0 4 CH27 0 3 CH26 0 2 CH25 0 1 CH24 0 0 CH23 0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 22 to 30 (CH23 to CH30). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel
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15.2.3 Software Signaling Insertion-Enable Registers, T1 Mode In T1 mode, only registers SSIE1-SSIE3 are used since there are only 24 channels in a T1 frame.
Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 1 to 8 (CH1 to CH8). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 SSIE2 Software Signaling-Insertion Enable 2 09h 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 9 to 16 (CH9 to CH16). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 SSIE3 Software Signaling-Insertion Enable 3 0Ah 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Software Signaling Insertion Enable for Channels 17 to 24 (CH17 to CH24). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel
15.2.4 Hardware-Based Mode In hardware-based mode, signaling data is input through the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data can be inserted on a per-channel basis by the transmit hardware-signaling channel-select (THSCS) function. The user has the ability to control which channels are to have signaling data from the TSIG pin inserted into them on a per-channel basis. See Section 5 for details on using this per-channel (THSCS) feature. The signaling insertion capabilities of the framer are available whether the transmitside elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz. Also, if the elastic is enabled in conjunction with transmit hardware signaling, CCR3.7 must be set = 0.
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16.
PER-CHANNEL IDLE CODE GENERATION
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the DS2156, the remaining channels, CH25-CH32, are not used. The DS2156 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR). The contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. This substitution can be enabled and disabled on a perchannel basis by the transmit-channel idle code-enable registers (TCICE1-4) and receive-channel idle code-enable registers (RCICE1-4). To program idle codes, first select a channel by writing to the IAAR register. Then write the idle code to the PCICR register. For successive writes there is no need to load the IAAR with the next consecutive address. The IAAR register automatically increments after a write to the PCICR register. The auto increment feature can be used for read operations as well. Bits 6 and 7 of the IAAR register can be used to block write a common idle code to all transmit or receive positions in the array with a single write to the PCICR register. Bits 6 and 7 of the IAAR register should not be used for read operations. TCICE1-4 and RCICE1-4 are used to enable idle code replacement on a per-channel basis.
Table 16-A. Idle-Code Array Address Mapping
BITS 0 to 5 OF IAAR REGISTER 0 1 2 -- -- 30 31 32 33 34 -- -- 62 63 MAPS TO CHANNEL Transmit Channel 1 Transmit Channel 2 Transmit Channel 3 -- -- Transmit Channel 31 Transmit Channel 32 Receive Channel 1 Receive Channel 2 Receive Channel 3 -- -- Receive Channel 31 Receive Channel 32
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16.1 Idle-Code Programming Examples
Example 1
Sets transmit channel 3 idle code to 7Eh.
Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh
Example 2
Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of idle codes for those channels.
Write Write Write Write Write Write IAAR = 02h PCICR = 7Eh PCICR = 7Eh PCICR = 7Eh PCICR = 7Eh TCICE1 = 3Ch ;select channel 3 in the array ;set channel 3 idle code to 7Eh ;set channel 4 idle code to 7Eh ;set channel 5 idle code to 7Eh ;set channel 6 idle code to 7Eh ;enable transmission of idle codes for channels 3,4,5, and 6
Example 3
Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh, EEh, FFh, and 7Eh, respectively.
Write Write Write Write Write IAAR = 02h PCICR = 7Eh PCICR = EEh PCICR = FFh PCICR = 7Eh
Example 4
Sets all transmit idle codes to 7Eh.
Write IAAR = 4xh Write PCICR = 7Eh
Example 5
Sets all receive and transmit idle codes to 7Eh and enables idle code substitution in all E1 transmit and receive channels.
Write IAAR = Cxh Write PCICR = 7Eh Write TCICE1 = FEh ;enable block write to all transmit and receive positions in the array ;7Eh is idle code ;enable idle code substitution for transmit channels 2 through 8 ;Although an idle code was programmed for channel 1 by the block write ;function above, enabling it for channel 1 would step on the frame ;alignment, alarms, and Sa bits ;enable idle code substitution for transmit channels 9 through 16 ;enable idle code substitution for transmit channels 18 through 24 ;Although an idle code was programmed for channel 17 by the block write ;function above, enabling it for channel 17 would step on the CAS frame ;alignment, and signaling information ;enable idle code substitution for transmit channels 25 through 32 ;enable idle code substitution for receive channels 2 through 8 ;enable idle code substitution for receive channels 9 through 16 ;enable idle code substitution for receive channels 18 through 24 ;enable idle code substitution for receive channels 25 through 32
Write TCICE2 = FFh Write TCICE3 = FEh
Write Write Write Write Write
TCICE4 RCICE1 RCICE2 RCICE3 RCICE4
= = = = =
FFh FEh FFh FEh FFh
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 GRIC 0 IAAR Idle Array Address Register 7Eh 6 GTIC 0 5 IAA5 0 4 IAA4 0 3 IAA3 0 2 IAA2 0 1 IAA1 0 0 IAA0 0
Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed with the idle code defined in the PCICR register. IAA0 is the LSB of the 5-bit channel code. Channel 1 is 01h. Bit 6/Global Transmit-Idle Code (GTIC). Setting this bit causes all transmit channels to be set to the idle code written to the PCICR register. This bit must be set = 0 for read operations. The value in bits IAA0-IAA5 must be a valid transmit channel (01h to 20h for E1 mode; 01h to 18h for T1 mode). Bit 7/Global Receive-Idle Code (GRIC). Setting this bit causes all receive channels to be set to the idle code written to the PCICR register. This bit must be set = 0 for read operations. The value in bits IAA0-IAA5 must be a valid transmit channel (01h to 20h for E1 mode; 01h to 18h for T1 mode).
Table 16-B. GRIC and GTIC Functions
GRIC 0 0 1 1 GTIC 0 1 0 1 FUNCTION Updates a single transmit or receive channel Updates all transmit channels Updates all receive channels Updates all transmit and receive channels
Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0
PCICR Per-Channel Idle Code Register 7Fh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bits 0 to 7/Per-Channel Idle-Code Bits (C0 to C7). This register defines the idle code to be programmed in the channel selected by the IAAR register. C0 is the LSB of the idle code (this bit is transmitted last).
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DS2156 The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel code array. Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 TCICE1 Transmit-Channel Idle-Code Enable Register 1 80h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Transmit Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle-code array into the transmit data stream Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 TCICE2 Transmit-Channel Idle-Code Enable Register 2 81h 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Transmit Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-array into the transmit data stream Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 TCICE3 Transmit-Channel Idle-Code Enable Register 3 82h 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle code-array into the transmit data stream Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 TCICE4 Transmit-Channel Idle-Code Enable Register 4 83h 6 CH31 0 5 CH30 0 4 CH29 0 3 CH28 0 2 CH27 0 1 CH26 0 0 CH25 0
Bits 0 to 7/Transmit Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32) 0 = do not insert data from the idle-code array into the transmit data stream 1 = insert data from the idle-code array into the transmit data stream 105 of 262
DS2156 The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel code array. Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 RCICE1 Receive-Channel Idle-Code Enable Register 1 84h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Receive Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 RCICE2 Receive-Channel Idle-Code Enable Register 2 85h 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 RCICE3 Receive-Channel Idle-Code Enable Register 3 86h 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 RCICE4 Receive-Channel Idle-Code Enable Register 4 87h 6 CH31 0 5 CH30 0 4 CH29 0 3 CH28 0 2 CH27 0 1 CH26 0 0 CH25 0
Bits 0 to 7/Receive Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32) 0 = do not insert data from the idle-code array into the receive data stream 1 = insert data from the idle-code array into the receive data stream
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17.
CHANNEL BLOCKING REGISTERS
The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. Channels 25 through 32 are ignored when the DS2156 is operated in the T1 mode.
Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 RCBR1 Receive Channel Blocking Register 1 88h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Receive Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 RCBR2 Receive Channel Blocking Register 2 89h 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Receive Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 RCBR3 Receive Channel Blocking Register 3 8Ah 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Receive Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 RCBR4 Receive Channel Blocking Register 4 8Bh 6 CH31 0 5 CH30 0 4 CH29 0 3 CH28 0 2 CH27 0 1 CH26 0 0 CH25 0
Bits 0 to 7/Receive Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 TCBR1 Transmit Channel Blocking Register 1 8Ch 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0
Bits 0 to 7/Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 TCBR2 Transmit Channel Blocking Register 2 8Dh 6 CH15 0 5 CH14 0 4 CH13 0 3 CH12 0 2 CH11 0 1 CH10 0 0 CH9 0
Bits 0 to 7/Transmit Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 TCBR3 Transmit Channel Blocking Register 3 8Eh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0
Bits 0 to 7/Transmit Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 TCBR4 Transmit Channel Blocking Register 4 8Fh 6 CH31 0 5 CH30 0 4 CH29 0 3 CH28 0 2 CH27 0 1 CH26 0 0 CH25 0
Bits 0 to 7/Transmit Channels 25 to 32 Channel Blocking Control Bits (CH25 to CH32) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time
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18.
ELASTIC STORES OPERATION
The elastic store function is unavailable when UTOPIA backplane is enabled. The DS2156 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled independently of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate the other elastic store is interfacing to. The elastic stores have two main purposes. Firstly, they can be used for rate conversion. When the DS2156 is in the T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic store can rate-convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates, which is the IBO discussed in Section 28.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TESALGN 0 ESCR Elastic Store Control Register 4Fh 6 TESR 0 5 TESMDM 0 4 TESE 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0
Bit 0/Receive Elastic Store Enable (RESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1/Receive Elastic Store Minimum-Delay Mode (RESMDM). See Section 18.4 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth Bit 2/Receive Elastic Store Reset (RESR). Setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the receive elastic store. It should be toggled after RSYSCLK has been applied and is stable. See Section 18.3 for details. Do not leave this bit set HIGH. Bit 3/Receive Elastic Store Align (RESALGN). Setting this bit from a 0 to a 1 forces the receive elastic store's write/read pointers to a minimum separation of half a frame. No action is taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed and the data is disrupted. It should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 18.3 for details. Bit 4/Transmit Elastic Store Enable (TESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 5/Transmit Elastic Store Minimum-Delay Mode (TESMDM). See Section 18.4 for details. 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth Bit 6/Transmit Elastic Store Reset (TESR). Setting this bit from a 0 to a 1 forces the read and write pointers into opposite frames, maximizing the delay through the transmit elastic store. Transmit data is lost during the reset. It should be toggled after TSYSCLK has been applied and is stable. See Section 18.3 for details. Do not leave this bit set HIGH. Bit 7/Transmit Elastic Store Align (TESALGN). Setting this bit from a 0 to a 1 forces the transmit elastic store's write/read pointers to a minimum separation of half a frame. No action is taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed and the data is disrupted. It should be toggled after TSYSCLK has been applied and is stable. It must be cleared and set again for a subsequent align. See Section 18.3 for details.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 SR5 Status Register 5 1Eh 6 -- 0 5 TESF 0 4 TESEM 0 3 TSLIP 0 2 RESF 0 1 RESEM 0 0 RSLIP 0
Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 1/Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated. Bit 2/Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted. Bit 3/Transmit Elastic Store Slip-Occurrence Event (TSLIP). Set when the transmit elastic store has either repeated or deleted a frame. Bit 4/Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated. Bit 5/Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 IMR5 Interrupt Mask Register 5 1Fh 6 -- 0 5 TESF 0 4 TESEM 0 3 TSLIP 0 2 RESF 0 1 RESEM 0 0 RSLIP 0
Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP) 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive Elastic Store Empty Event (RESEM) 0 = interrupt masked 1 = interrupt enabled Bit 2/Receive Elastic Store Full Event (RESF) 0 = interrupt masked 1 = interrupt enabled Bit 3/Transmit Elastic Store Slip-Occurrence Event (TSLIP) 0 = interrupt masked 1 = interrupt enabled Bit 4/Transmit Elastic Store Empty Event (TESEM) 0 = interrupt masked 1 = interrupt enabled Bit 5/Transmit Elastic Store Full Event (TESF) 0 = interrupt masked 1 = interrupt enabled 112 of 262
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18.1 Receive Side
See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system clock applications, see the Interleaved PCM Bus Operation in Section 28. The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If signaling reinsertion is enabled, signaling data in TS16 is realigned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer always indicates frame boundaries on the network side of the elastic store by the RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries are always indicated by the RMSYNC output. If the elastic store is enabled, then RMSYNC outputs the multiframe boundary on the backplane side of the elastic store. 18.1.1 T1 Mode If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the data output at RSER is forced to all 1s every fourth channel and the F-bit is passed into the MSB of TS0. Hence, channels 1 (bits 1-7), 5, 9, 13, 17, 21, 25, and 29 [time slots 0 (bits 1-7), 4, 8, 12, 16, 20, 24, and 28] are forced to a 1. Also, in 2.048MHz applications, the RCHBLK output is forced high during the same channels as the RSER pin. This is useful in T1-to-E1 conversion applications. If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, then a full frame of data is repeated at RSER, and the SR5.0 and SR5.1 bits are set to a 1. If the buffer fills, then a full frame of data is deleted, and the SR5.0 and SR5.2 bits are set to a 1. 18.1.2 E1 Mode If the elastic store is enabled, then either CAS or CRC4 multiframe boundaries are indicated through the RMSYNC output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth channel of the received E1 data is deleted and an F-bit position, which is forced to 1, is inserted. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are deleted from the received E1 data stream. Also, in 1.544MHz applications, the RCHBLK output is not active in channels 25 through 32 (i.e., RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, then a full frame of data is repeated at RSER, and the SR5.0 and SR5.1 bits are set to a 1. If the buffer fills, then a full frame of data is deleted, and the SR5.0 and SR5.2 bits are set to a 1.
18.2 Transmit Side
See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled, a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher rate system clock applications, see Interleaved PCM Bus Operation in Section 28. Controlled slips in the transmit elastic store are reported in the SR5.3 bit, and the direction of the slip is reported in the SR5.4 and SR5.5 bits. If hardware signaling insertion is not enabled, CCR3.7 should be set = 1.
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18.2.1 T1 Mode If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER is ignored every fourth channel. Therefore channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are ignored. The user can supply frame or multiframe sync pulse to the TSSYNC input. Also, in 2.048MHz applications, the TCHBLK output is forced high during the channels ignored by the framer. 18.2.2 E1 Mode A 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame sync pulse or a multiframe sync pulse to the TSSYNC input.
18.3 Elastic Stores Initialization
There are two elastic store initializations that can be used to improve performance in certain applications, elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store's read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK, respectively) (Table 18-A).
Table 18-A. Elastic Store Delay After Initialization
INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align REGISTER BIT ESCR.2 ESCR.6 ESCR.3 ESCR.7 DELAY 8 Clocks < Delay < 1 Frame 1 Frame < Delay < 2 Frames 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames
18.4 Minimum Delay Mode
Elastic store minimum delay mode can be used when the elastic store's system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). ESCR.5 and ESCR.1 enable the transmit and receive elastic store minimum delay modes. When enabled, the elastic stores are forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode; TSYNC must be configured as an output when transmit minimum delay mode is enabled. In a typical application, RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bits (ESCR.2 and ESCR.6) should be toggled from a 0 to a 1 to ensure proper operation.
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19.
G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)
The DS2156 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This change in data content is used to modify the CRC-4 checksum. This modification, however, does not corrupt any error information the original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode. The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input, then the user must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe-align the data presented to TSER.
Figure 19-1. CRC-4 Recalculate Method
TPOSO/TNEGO
INSERT NEW CRC-4 CODE
EXTRACT OLD CRC-4 CODE
TSER
+
CRC-4 CALCULATOR
XOR
MODIFY Sa BIT POSITIONS
NEW Sa BIT DATA
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20.
T1 BIT-ORIENTED CODE (BOC) CONTROLLER
The DS2156 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode.
20.1 Transmit BOC
Bits 0 to 5 in the TFDL register contain the BOC message to be transmitted. Setting BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages are transmitted as long as BOCC.0 is set. Transmit a BOC 1) Write 6-bit code into the TFDL register. 2) Set the SBOC bit in BOCC = 1.
20.2 Receive BOC
The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register now operates as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are preset to all 1s. When the BOC bits change state, the BOC change-of-state indicator, SR8.0, alerts the host. The host then reads the RFDL register to get the BOC status and message. A change-ofstate occurs when either a new BOC code has been present for a time determined by the receive BOC filter bits RBF0 and RBF1 in the BOCC register, or a nonvalid code is being received. Receive a BOC 1) Set integration time through BOCC.1 and BOCC.2. 2) Enable the receive BOC function (BOCC.4 = 1). 3) Enable interrupt (IMR8.0 = 1). 4) Wait for interrupt to occur. 5) Read the RFDL register. 6) If SR2.7 = 1, then a valid BOC message was received. - The lower six bits of the RFDL register comprise the message.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 BOCC BOC Control Register 37h 6 -- 0 5 -- 0 4 RBOCE 0 3 RBR 0 2 RBF1 0 1 RBF0 0 0 SBOC 0
Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register. Bits 1 and 2/Receive BOC Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. RBF1 0 0 1 1 RBF0 0 1 0 1 Consecutive BOC Codes for Valid Sequence Identification None 3 5 7
Bit 3/Receive BOC Reset (RBR). A 0-to-1 transition resets the BOC circuitry. Must be cleared and set again for a subsequent reset. Bit 4/Receive BOC Enable (RBOCE). Enables the receive BOC function. The RFDL register reports the received BOC code and two information bits when this bit is set. 0 = receive BOC function disabled 1 = receive BOC function enabled; the RFDL register reports BOC messages and information Bits 5 to 7/Unused, must be set to 0 for proper operation
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
RFDL Receive FDL Register C0h 6 -- 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0
RFDL register bit definitions when BOCC.4 = 1: Bit 0/BOC Bit 0 (RBOC0) Bit 1/BOC Bit 1 (RBOC1) Bit 2/BOC Bit 2 (RBOC2) Bit 3/BOC Bit 3 (RBOC3) Bit 4/BOC Bit 4 (RBOC4) Bit 5/BOC Bit 5 (RBOC5) Bits 6, 7/This bit position is unused when BOCC.4 = 1. 117 of 262
DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 SR8 Status Register 8 24h 6 -- 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0
Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a valid BOC. The setting of this bit prompts the user to read the RFDL register. Bit 1/Receive FDL Match Event (RMTCH). Set whenever the contents of the RFDL register matches RFDLM1 or RFDLM2. Bit 2/TFDL Register Empty Event (TFDLE). Set when the transmit FDL buffer (TFDL) empties. Bit 3/RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (RFDL) fills to capacity. Bit 4/RFDL Abort Detect Event (RFDLAD). Set when eight consecutive 1s are received on the FDL. Bit 5/BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 6 -- 0
IMR8 Interrupt Mask Register 8 25h 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0
Bit 0/Receive BOC Detector Change-of-State Event (RBOC) 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive FDL Match Event (RMTCH) 0 = interrupt masked 1 = interrupt enabled Bit 2/TFDL Register Empty Event (TFDLE) 0 = interrupt masked 1 = interrupt enabled Bit 3/RFDL Register Full Event (RFDLF) 0 = interrupt masked 1 = interrupt enabled Bit 4/RFDL Abort Detect Event (RFDLAD) 0 = interrupt masked 1 = interrupt enabled Bit 5/BOC Clear Event (BOCC) 0 = interrupt masked 1 = interrupt enabled
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21. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)
When operated in the E1 mode, the DS2156 provides three methods for accessing the Sa and the Si bits. The first method involves a hardware scheme that uses the RLINK/RLCLK and TLINK/TLCLK pins (Section 21.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers (Section 21.2). The third method, which is covered in Section 21.3, involves an expanded version of the second method.
21.1 Method 1: Hardware Scheme
On the receive side, all of the received data is reported at the RLINK pin. Using the E1RCR2 register, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it identifies the Si bits. On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (Section 21.2) or externally from the TLINK pin. Using the E1TCR2 register, the framer can be programmed to source any combination of the Sa bits from the TLINK pin. Si bits can be sampled through the TSER pin if by setting E1TCR1.4 = 0.
21.2 Method 2: Internal Register Scheme Based on Double-Frame
On the receive side, the RAF and RNAF registers always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on align-frame boundaries. The setting of the receive align frame bit in Status Register 4 (SR4.0) indicates that the contents of the RAF and RNAF have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers. The host has 250s to retrieve the data before it is lost. On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the transmit align frame bit in Status Register 4 (SR4.3). The host can use the SR4.3 bit to know when to update the TAF and TNAF registers. It has 250s to update the data or else the old data is retransmitted. If the TAF and TNAF registers are only being used to source the align frame and nonalign frame-sync patterns, then the host need only write once to these registers. Data in the Si bit position is overwritten if either the framer is (1) programmed to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) has automatic E-bit insertion enabled. Data in the Sa bit position is overwritten if any of the E1TCR2.3 to E1TCR2.7 bits are set to 1.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 RAF Receive Align Frame Register C6h 6 0 0 5 0 0 4 1 0 3 1 0 2 0 0 1 1 0 0 1 0
Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) Bit 3/Frame Alignment Signal Bit (1) Bit 4/Frame Alignment Signal Bit (1) Bit 5/Frame Alignment Signal Bit (0) Bit 6/Frame Alignment Signal Bit (0) Bit 7/International Bit (Si)
Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0
RNAF Receive Nonalign Frame Register C7h 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0
Bit 0/Additional Bit 8 (Sa8) Bit 1/Additional Bit 7 (Sa7) Bit 2/Additional Bit 6 (Sa6) Bit 3/Additional Bit 5 (Sa5) Bit 4/Additional Bit 4 (Sa4) Bit 5/Remote Alarm (A) Bit 6/Frame Nonalignment Signal Bit (1) Bit 7/International Bit (Si)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 TAF Transmit Align Frame Register D0h 6 0 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1
Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) Bit 3/Frame Alignment Signal Bit (1) Bit 4/Frame Alignment Signal Bit (1) Bit 5/Frame Alignment Signal Bit (0) Bit 6/Frame Alignment Signal Bit (0) Bit 7/International Bit (Si)
Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0
TNAF Transmit Nonalign Frame Register D1h 6 1 1 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0
Bit 0/Additional Bit 8 (Sa8) Bit 1/Additional Bit 7 (Sa7) Bit 2/Additional Bit 6 (Sa6) Bit 3/Additional Bit 5 (Sa5) Bit 4/Additional Bit 4 (Sa4) Bit 5/Remote Alarm [used to transmit the alarm (A)] Bit 6/Frame Nonalignment Signal Bit (1) Bit 7/International Bit (Si)
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21.3 Method 3: Internal Register Scheme Based on CRC4 Multiframe
The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4-RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC4 multiframe bit in Status Register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first received. See the following register descriptions for more details. The transmit side also contains a set of eight registers (TSiAF, TSiNAF, TRA, and TSa4-TSa8) that, through the transmit Sa bit control register (TSaCR), can be programmed to insert Si and Sa data. Data is sampled from these registers with the setting of the transmit multiframe bit in Status Register 2 (SR4.4). The host can use the SR4.4 bit to know when to update these registers. It has 2ms to update the data or else the old data is retransmitted. The MSB of each register is the first bit transmitted. See the following register descriptions for more details.
Register Name: Register Description: Register Address: Bit # Name Default 7 SiF14 0 RSiAF Received Si Bits of the Align Frame C8h 6 SiF12 0 5 SiF10 0 4 SiF8 0 3 SiF6 0 2 SiF4 0 1 SiF2 0 0 SiF0 0
Bit 0/Si Bit of Frame 0 (SiF0) Bit 1/Si Bit of Frame 2 (SiF2) Bit 2/Si Bit of Frame 4 (SiF4) Bit 3/Si Bit of Frame 6 (SiF6) Bit 4/Si Bit of Frame 8 (SiF8) Bit 5/Si Bit of Frame 10 (SiF10) Bit 6/Si Bit of Frame 12 (SiF12) Bit 7/Si Bit of Frame 14 (SiF14)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 SiF15 0 RSiNAF Received Si Bits of the Nonalign Frame C9h 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0
Bit 0/Si Bit of Frame 1 (SiF1) Bit 1/Si Bit of Frame 3 (SiF3) Bit 2/Si Bit of Frame 5 (SiF5) Bit 3/Si Bit of Frame 7 (SiF7) Bit 4/Si Bit of Frame 9 (SiF9) Bit 5/Si Bit of Frame 11 (SiF11) Bit 6/Si Bit of Frame 13 (SiF13) Bit 7/Si Bit of Frame 15 (SiF15) Register Name: Register Description: Register Address: Bit # Name Default 7 RRAF15 0 RRA Received Remote Alarm Cah 6 RRAF13 0 5 RRAF11 0 4 RRAF9 0 3 RRAF7 0 2 RRAF5 0 1 RRAF3 0 0 RRAF1 0
Bit 0/Remote Alarm Bit of Frame 1 (RRAF1) Bit 1/Remote Alarm Bit of Frame 3 (RRAF3) Bit 2/Remote Alarm Bit of Frame 5 (RRAF5) Bit 3/Remote Alarm Bit of Frame 7 (RRAF7) Bit 4/Remote Alarm Bit of Frame 9 (RRAF9) Bit 5/Remote Alarm Bit of Frame 11 (RRAF11) Bit 6/Remote Alarm Bit of Frame 13 (RRAF13) Bit 7/Remote Alarm Bit of Frame 15 (RRAF15)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F15 0 RSa4 Received Sa4 Bits CBh 6 RSa4F13 0 5 RSa4F11 0 4 RSa4F9 0 3 RSa4F7 0 2 RSa4F5 0 1 RSa4F3 0 0 RSa4F1 0
Bit 0/Sa4 Bit of Frame 1 (RSa4F1) Bit 1/Sa4 Bit of Frame 3 (RSa4F3) Bit 2/Sa4 Bit of Frame 5 (RSa4F5) Bit 3/Sa4 Bit of Frame 7 (RSa4F7) Bit 4/Sa4 Bit of Frame 9 (RSa4F9) Bit 5/Sa4 Bit of Frame 11 (RSa4F11) Bit 6/Sa4 Bit of Frame 13 (RSa4F13) Bit 7/Sa4 Bit of Frame 15 (RSa4F15)
Register Name: Register Description: Register Address: Bit # Name Default 7 RSa5F15 0
RSa5 Received Sa5 Bits CCh 6 RSa5F13 0 5 RSa5F11 0 4 RSa5F9 0 3 RSa5F7 0 2 RSa5F5 0 1 RSa5F3 0 0 RSa5F1 0
Bit 0/Sa5 Bit of Frame 1 (RSa5F1) Bit 1/Sa5 Bit of Frame 3 (RSa5F3) Bit 2/Sa5 Bit of Frame 5 (RSa5F5) Bit 3/Sa5 Bit of Frame 7 (RSa5F7) Bit 4/Sa5 Bit of Frame 9 (RSa5F9) Bit 5/Sa5 Bit of Frame 11 (RSa5F11) Bit 6/Sa5 Bit of Frame 13 (RSa5F13) Bit 7/Sa5 Bit of Frame 15 (RSa5F15)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F15 0 RSa6 Received Sa6 Bits CDh 6 RSa6F13 0 5 RSa6F11 0 4 RSa6F9 0 3 RSa6F7 0 2 RSa6F5 0 1 RSa6F3 0 0 RSa6F1 0
Bit 0/Sa6 Bit of Frame 1 (RSa6F1) Bit 1/Sa6 Bit of Frame 3 (RSa6F3) Bit 2/Sa6 Bit of Frame 5 (RSa6F5) Bit 3/Sa6 Bit of Frame 7 (RSa6F7) Bit 4/Sa6 Bit of Frame 9 (RSa6F9) Bit 5/Sa6 Bit of Frame 11 (RSa6F11) Bit 6/Sa6 Bit of Frame 13 (RSa6F13) Bit 7/Sa6 Bit of Frame 15 (RSa6F15)
Register Name: Register Description: Register Address: Bit # Name Default 7 RSa7F15 0
RSa7 Received Sa7 Bits CEh 6 Rsa7F13 0 5 RSa7F11 0 4 RSa7F9 0 3 RSa7F7 0 2 RSa7F5 0 1 RSa7F3 0 0 RSa7F1 0
Bit 0/Sa7 Bit of Frame 1 (RSa7F1) Bit 1/Sa7 Bit of Frame 3 (RSa7F3) Bit 2/Sa7 Bit of Frame 5 (RSa7F5) Bit 3/Sa7 Bit of Frame 7 (RSa7F7) Bit 4/Sa7 Bit of Frame 9 (RSa7F9) Bit 5/Sa7 Bit of Frame 11 (RSa7F11) Bit 6/Sa7 Bit of Frame 13 (RSa7F13) Bit 7/Sa7 Bit of Frame 15 (RSa4F15)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F15 0 RSa8 Received Sa8 Bits CFh 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0
Bit 0/Sa8 Bit of Frame 1 (RSa8F1) Bit 1/Sa8 Bit of Frame 3 (RSa8F3) Bit 2/Sa8 Bit of Frame 5 (RSa8F5) Bit 3/Sa8 Bit of Frame 7 (RSa8F7) Bit 4/Sa8 Bit of Frame 9 (RSa8F9) Bit 5/Sa8 Bit of Frame 11 (RSa8F11) Bit 6/Sa8 Bit of Frame 13 (RSa8F13) Bit 7/Sa8 Bit of Frame 15 (RSa8F15)
Register Name: Register Description: Register Address: Bit # Name Default 7 TSiF14 0
TSiAF Transmit Si Bits of the Align Frame D2h 6 TSiF12 0 5 TSiF10 0 4 TSiF8 0 3 TSiF6 0 2 TSiF4 0 1 TSiF2 0 0 TSiF0 0
Bit 0/Si Bit of Frame 0 (TSiF0) Bit 1/Si Bit of Frame 2 (TSiF2) Bit 2/Si Bit of Frame 4 (TSiF4) Bit 3/Si Bit of Frame 6 (TSiF6) Bit 4/Si Bit of Frame 8 (TSiF8) Bit 5/Si Bit of Frame 10 (TSiF10) Bit 6/Si Bit of Frame 12 (TSiF12) Bit 7/Si Bit of Frame 14 (TSiF14)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TSiF15 0 TSiNAF Transmit Si Bits of the Nonalign Frame D3h 6 TSiF13 0 5 TSiF11 0 4 TSiF9 0 3 TSiF7 0 2 TSiF5 0 1 TSiF3 0 0 TSiF1 0
Bit 0/Si Bit of Frame 1 (TSiF1) Bit 1/Si Bit of Frame 3 (TSiF3) Bit 2/Si Bit of Frame 5 (TSiF5) Bit 3/Si Bit of Frame 7 (TSiF7) Bit 4/Si Bit of Frame 9 (TSiF9) Bit 5/Si Bit of Frame 11 (TSiF11) Bit 6/Si Bit of Frame 13 (TSiF13) Bit 7/Si Bit of Frame 15 (TSiF15)
Register Name: Register Description: Register Address: Bit # Name Default 7 TRAF15 0
TRA Transmit Remote Alarm D4h 6 TRAF13 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0
Bit 0/Remote Alarm Bit of Frame 1 (TRAF1) Bit 1/Remote Alarm Bit of Frame 3 (TRAF3) Bit 2/Remote Alarm Bit of Frame 5 (TRAF5) Bit 3/Remote Alarm Bit of Frame 7 (TRAF7) Bit 4/Remote Alarm Bit of Frame 9 (TRAF9) Bit 5/Remote Alarm Bit of Frame 11 (TRAF11) Bit 6/Remote Alarm Bit of Frame 13 (TRAF13) Bit 7/Remote Alarm Bit of Frame 15 (TRAF15)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TSa4F15 0 TSa4 Transmit Sa4 Bits D5h 6 TSa4F13 0 5 TSa4F11 0 4 TSa4F9 0 3 TSa4F7 0 2 TSa4F5 0 1 TSa4F3 0 0 TSa4F1 0
Bit 0/Sa4 Bit of Frame 1 (TSa4F1) Bit 1/Sa4 Bit of Frame 3 (TSa4F3) Bit 2/Sa4 Bit of Frame 5 (TSa4F5) Bit 3/Sa4 Bit of Frame 7 (TSa4F7) Bit 4/Sa4 Bit of Frame 9 (TSa4F9) Bit 5/Sa4 Bit of Frame 11 (TSa4F11) Bit 6/Sa4 Bit of Frame 13 (TSa4F13) Bit 7/Sa4 Bit of Frame 15 (TSa4F15)
Register Name: Register Description: Register Address: Bit # Name Default 7 TSa5F15 0
TSa5 Transmitted Sa5 Bits D6h 6 TSa5F13 0 5 TSa5F11 0 4 TSa5F9 0 3 TSa5F7 0 2 TSa5F5 0 1 TSa5F3 0 0 TSa5F1 0
Bit 0/Sa5 Bit of Frame 1 (TSa5F1) Bit 1/Sa5 Bit of Frame 3 (TSa5F3) Bit 2/Sa5 Bit of Frame 5 (TSa5F5) Bit 3/Sa5 Bit of Frame 7 (TSa5F7) Bit 4/Sa5 Bit of Frame 9 (TSa5F9) Bit 5/Sa5 Bit of Frame 11 (TSa5F11) Bit 6/Sa5 Bit of Frame 13 (TSa5F13) Bit 7/Sa5 Bit of Frame 15 (TSa5F15)
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Register Name: Register Description: Register Address: Bit # Name Default 7 TSa6F15 0
TSa6 Transmit Sa6 Bits D7h 6 TSa6F13 0 5 TSa6F11 0 4 TSa6F9 0 3 TSa6F7 0 2 TSa6F5 0 1 TSa6F3 0 0 TSa6F1 0
Bit 0/Sa6 Bit of Frame 1 (TSa6F1) Bit 1/Sa6 Bit of Frame 3 (TSa6F3) Bit 2/Sa6 Bit of Frame 5 (TSa6F5) Bit 3/Sa6 Bit of Frame 7 (TSa6F7) Bit 4/Sa6 Bit of Frame 9 (TSa6F9) Bit 5/Sa6 Bit of Frame 11 (TSa6F11) Bit 6/Sa6 Bit of Frame 13 (TSa6F13) Bit 7/Sa6 Bit of Frame 15 (TSa6F15)
Register Name: Register Description: Register Address: Bit # Name Default 7 TSa7F15 0
TSa7 Transmit Sa7 Bits D8h 6 TSa7F13 0 5 TSa7F11 0 4 TSa7F9 0 3 TSa7F7 0 2 TSa7F5 0 1 TSa7F3 0 0 TSa7F1 0
Bit 0/Sa7 Bit of Frame 1 (TSa7F1) Bit 1/Sa7 Bit of Frame 3 (TSa7F3) Bit 2/Sa7 Bit of Frame 5 (TSa7F5) Bit 3/Sa7 Bit of Frame 7 (TSa7F7) Bit 4/Sa7 Bit of Frame 9 (TSa7F9) Bit 5/Sa7 Bit of Frame 11 (TSa7F11) Bit 6/Sa7 Bit of Frame 13 (TSa7F13) Bit 7/Sa7 Bit of Frame 15 (TSa4F15)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TSa8F15 0 TSa8 Transmit Sa8 Bits D9h 6 TSa8F13 0 5 TSa8F11 0 4 TSa8F9 0 3 TSa8F7 0 2 TSa8F5 0 1 TSa8F3 0 0 TSa8F1 0
Bit 0/Sa8 Bit of Frame 1 (TSa8F1) Bit 1/Sa8 Bit of Frame 3 (TSa8F3) Bit 2/Sa8 Bit of Frame 5 (TSa8F5) Bit 3/Sa8 Bit of Frame 7 (TSa8F7) Bit 4/Sa8 Bit of Frame 9 (TSa8F9) Bit 5/Sa8 Bit of Frame 11 (TSa8F11) Bit 6/Sa8 Bit of Frame 13 (TSa8F13) Bit 7/Sa8 Bit of Frame 15 (TSa8F15)
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 TSACR Transmit Sa Bit Control Register DAh 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0
Bit 0/Additional Bit 8 Insertion Control Bit (Sa8) 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Bit 1/Additional Bit 7 Insertion Control Bit (Sa7) 0 = do not insert data from the TSa7 register into the transmit data stream 1 = insert data from the TSa7 register into the transmit data stream Bit 2/Additional Bit 6 Insertion Control Bit (Sa6) 0 = do not insert data from the TSa6 register into the transmit data stream 1 = insert data from the TSa6 register into the transmit data stream Bit 3/Additional Bit 5 Insertion Control Bit (Sa5) 0 = do not insert data from the TSa5 register into the transmit data stream 1 = insert data from the TSa5 register into the transmit data stream Bit 4/Additional Bit 4 Insertion Control Bit (Sa4) 0 = do not insert data from the TSa4 register into the transmit data stream 1 = insert data from the TSa4 register into the transmit data stream Bit 5/Remote Alarm Insertion Control Bit (RA) 0 = do not insert data from the TRA register into the transmit data stream 1 = insert data from the TRA register into the transmit data stream Bit 6/International Bit in Nonalign Frame Insertion Control Bit (SiNAF) 0 = do not insert data from the TSiNAF register into the transmit data stream 1 = insert data from the TSiNAF register into the transmit data stream Bit 7/International Bit in Align Frame Insertion Control Bit (SiAF) 0 = do not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream
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22.
HDLC CONTROLLERS
This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte buffers in the transmit and receive paths. When used with time slots, the user can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the HDLC controllers. The user must not map both transmit HDLC controllers to the same Sa bits, time slots or, in T1 mode, map both controllers to the FDL. HDLC #1 and HDLC #2 are identical in operation and therefore the following operational description refers only to a singular controller. The HDLC controller performs the entire necessary overhead for generating and receiving performance report messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 128-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
22.1 Basic Operation Details
The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and FIFOs. Table 22-A lists these registers by group.
22.2 HDLC Configuration
The HxTC and HxRC registers perform the basic configuration of the HDLC controllers. Operating features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options, and idle flags are selected here. These registers also reset the HDLC controllers.
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Table 22-A. HDLC Controller Registers
REGISTER FUNCTION CONTROL AND CONFIGURATION H1TC, HDLC #1 Transmit Control Register General control over the transmit HDLC H2TC, HDLC #2 Transmit Control Register controllers H1RC, HDLC #1 Receive Control Register General control over the receive HDLC H2RC, HDLC #2 Receive Control Register controllers H1FC, HDLC #1 FIFO Control Register Sets high watermark for receiver and low H2FC, HDLC #2 FIFO Control Register watermark for transmitter STATUS AND INFORMATION SR6, HDLC #1 Status Register Key status information for both transmit and SR7, HDLC #2 Status Register receive directions IMR6, HDLC #1 Interrupt Mask Register Selects which bits in the status registers (SR7 IMR7, HDLC #2 Interrupt Mask Register and SR8) cause interrupts INFO4, HDLC #1 and #2 Information Register Information about HDLC controller INFO5, HDLC #1 Information Register INFO6, HDLC #2 Information Register H1RPBA, HDLC #1 Receive Packet Bytes Indicates the number of bytes that can be read Available Register from the receive FIFO H2RPBA, HDLC #2 Receive Packet Bytes Available Register H1TFBA, HDLC #1 Transmit FIFO Buffer Indicates the number of bytes that can be Available Register written to the transmit FIFO H2TFBA, HDLC #2 Transmit FIFO Buffer Available Register MAPPING H1RCS1, H1RCS2, H1RCS3, H1RCS4, HDLC Selects which channels are mapped to the #1 Receive Channel Select Registers receive HDLC controller H2RCS1, H2RCS2, H2RCS3, H2RCS4, HDLC #2 Receive Channel Select Registers H1RTSBS, HDLC #1 Receive TS/Sa Bit Select Selects which bits in a channel are used or Register which Sa bits are used by the receive HDLC H2RTSBS, HDLC #2 Receive TS/Sa Bit Select controller Register H1TCS1, H1TCS2, H1TCS3, H1TCS4, HDLC Selects which channels are mapped to the #1 Transmit Channel Select Registers transmit HDLC controller H2TCS1, H2TCS2, H2TCS3, H2TCS4, HDLC #2 Transmit Channel Select Registers H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select Selects which bits in a channel are used or Register which Sa bits are used by the transmit HDLC H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select controller Register FIFOs H1RF, HDLC #1 Receive FIFO Register Access to 128-byte receive FIFO H2RF, HDLC #1 Receive FIFO Register H1TF, HDLC #1 Transmit FIFO Register Access to 128-byte transmit FIFO H2TF, HDLC #2 Transmit FIFO Register
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 NOFS 0 H1TC, H2TC HDLC #1 Transmit Control HDLC #2 Transmit Control 90h, A0h 6 TEOML 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0
Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation Bit 1/Transmit Zero-Stuffer Defeat (TZSD). The zero-stuffer function automatically inserts a 0 in the message field (between the flags) after five consecutive 1s to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (destuffs) any 0 after five 1s in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Bit 2/Transmit End of Message (TEOM). Should be set to a 1 just before the last data byte of an HDLC packet is written into the transmit FIFO at HxTF. If not disabled through TCRCD, the transmitter automatically appends a 2byte CRC code to the end of the message. Bit 3/Transmit Flag/Idle Select (TFS). This bit selects the intermessage fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 4/Transmit HDLC Mapping Select (THMS) 0 = transmit HDLC assigned to channels 1 = transmit HDLC assigned to FDL (T1 mode), Sa bits (E1 mode) Bit 5/Transmit HDLC Reset (THR). Resets the transmit HDLC controller and flushes the transmit FIFO. An abort followed by 7Eh or FFh flags/idle is transmitted until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset transmit HDLC controller and flush the transmit FIFO Bit 6/Transmit End of Message and Loop (TEOML). To loop on a message, this bit should be set to a 1 just before the last data byte of an HDLC packet is written into the transmit FIFO. The message repeats until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message completes, then flags are transmitted until a new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO, the loop terminates, one or two flags are transmitted, and the new message starts. If not disabled through TCRCD, the transmitter automatically appends a 2-byte CRC code to the end of all messages. This is useful for transmitting consecutive SS7 FISUs without host intervention. Bit 7/Number of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RHR 0 H1RC, H2RC HDLC #1 Receive Control HDLC #2 Receive Control 31h, 32h 6 RHMS 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 RSFD 0
Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD) 0 = normal operation; all FISUs are stored in the receive FIFO and reported to the host. 1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without host intervention. Bits 1 to 5/Unused, must be set to 0 or proper operation Bit 6/Receive HDLC Mapping Select (RHMS) 0 = receive HDLC assigned to channels 1 = receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode) Bit 7/Receive HDLC Reset (RHR). Resets the receive HDLC controller and flushes the receive FIFO. Must be cleared and set again for a subsequent reset. 0 = normal operation 1 = reset receive HDLC controller and flush the receive FIFO
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22.2.1 FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register SR6 or SR7 is set. TLWM is a real-time bit and remains set as long as the transmit FIFO's read pointer is below the watermark. If enabled, this condition can also cause an interrupt through the INT pin. When the receive FIFO fills above the high watermark, the RHWM bit in the appropriate HDLC status register is set. RHWM is a real-time bit and remains set as long as the receive FIFO's write pointer is above the watermark. If enabled, this condition can also cause an interrupt through the INT pin.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 H1FC, H2FC HDLC # 1 FIFO Control HDLC # 2 FIFO Control 91h, A1h 6 -- 0 5 TFLWM2 0 4 TFLWM1 0 3 TFLWM0 0 2 RFHWM2 0 1 RFHWM1 0 0 RFHWM0 0
Bits 0 to 2/Receive FIFO High-Watermark Select (RFHWM0 to RFHWM2) RFHWM2 0 0 0 0 1 1 1 1 RFHWM1 0 0 1 1 0 0 1 1 RFHWM0 0 1 0 1 0 1 0 1 Receive FIFO Watermark (bytes) 4 16 32 48 64 80 96 112
Bits 3 to 5/Transmit FIFO Low-Watermark Select (TFLWM0 to TFLWM2) TFLWM2 0 0 0 0 1 1 1 1 TFLWM1 0 0 1 1 0 0 1 1 TFLWM0 0 1 0 1 0 1 0 1 Transmit FIFO Watermark (bytes) 4 16 32 48 64 80 96 112
Bits 6, 7/Unused, must be set to 0 for proper operation
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22.3 HDLC Mapping
22.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel(s), any combination of bits within the channel(s) can be avoided. The HxRCS1-HxRCS4 registers are used to assign the receive controllers to channels 1-24 (T1) or 1-32 (E1) according to the following table: Register HxRCS1 HxRCS2 HxRCS3 HxRCS4
Register Name: Register Description: Register Address: Bit # Name Default 7 RHCS7 0
Channels 1-8 9-16 17-24 25-32
H1RCS1, H1RCS2, H1RCS3, H1RCS4 H2RCS1, H2RCS2, H2RCS3, H2RCS4 HDLC # 1 Receive Channel Select x HDLC # 2 Receive Channel Select x 92h, 93h, 94h, 95h A2h, A3h, A4h, A5h 6 RHCS6 0 5 RHCS5 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0
Bit 0/Receive HDLC Channel Select Bit 0 (RHCS0). Select Channel 1, 9, 17, or 25. Bit 1/Receive HDLC Channel Select Bit 1 (RHCS1). Select Channel 2, 10, 18, or 26. Bit 2/Receive HDLC Channel Select Bit 2 (RHCS2). Select Channel 3, 11, 19, or 27. Bit 3/Receive HDLC Channel Select Bit 3 (RHCS3). Select Channel 4, 12, 20, or 28. Bit 4/Receive HDLC Channel Select Bit 4 (RHCS4). Select Channel 5, 13, 21, or 29. Bit 5/Receive HDLC Channel Select Bit 5 (RHCS5). Select Channel 6, 14, 22, or 30. Bit 6/Receive HDLC Channel Select Bit 6 (RHCS6). Select Channel 7, 15, 23, or 31. Bit 7/Receive HDLC Channel Select Bit 7 (RHCS7). Select Channel 8, 16, 24, or 32.
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Register Name: Register Description: Register Address: Bit # Name Default 7 RCB8SE 0
H1RTSBS, H2RTSBS HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h 6 RCB7SE 0 5 RCB6SE 0 4 RCB5SE 0 3 RCB4SE 0 2 RCB3SE 0 1 RCB2SE 0 0 RCB1SE 0
Bit 0/Receive Channel Bit 1 Suppress Enable/Sa8 Bit Enable (RCB1SE ). LSB of the channel. Set to 1 to stop this bit from being used. Bit 1/Receive Channel Bit 2 Suppress Enable/Sa7 Bit Enable (RCB2SE). Set to 1 to stop this bit from being used. Bit 2/Receive Channel Bit 3 Suppress Enable/Sa6 Bit Enable (RCB3SE). Set to 1 to stop this bit from being used. Bit 3/Receive Channel Bit 4 Suppress Enable/Sa5 Bit Enable (RCB4SE). Set to 1 to stop this bit from being used. Bit 4/Receive Channel Bit 5 Suppress Enable/Sa4 Bit Enable (RCB5SE). Set to 1 to stop this bit from being used. Bit 5/Receive Channel Bit 6 Suppress Enable (RCB6SE). Set to 1 to stop this bit from being used. Bit 6/Receive Channel Bit 7 Suppress Enable (RCB7SE). Set to 1 to stop this bit from being used. Bit 7/Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to 1 to stop this bit from being used.
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22.3.2 Transmit The HxTCS1-HxTCS4 registers are used to assign the transmit controllers to channels 1-24 (T1) or 1-32 (E1) according to the following table.
Register HxTCS1 HxTCS2 HxTCS3 HxTCS4 Register Name: Register Description: Register Address: Bit # Name Default 7 THCS7 0 Channels 1-8 9-16 17-24 25-32 H1TCS1, H1TCS2, H1TCS3, H1TCS4 H2TCS1, H2TCS2, H2TCS3, H2TCS4 HDLC # 1 Transmit Channel Select HDLC # 2 Transmit Channel Select 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh 6 THCS6 0 5 THCS5 0 4 THCS4 0 3 THCS3 0 2 THCS2 0 1 THCS1 0 0 THCS0 0
Bit 0/Transmit HDLC Channel Select Bit 0 (THCS0). Select Channel 1, 9, 17, or 25. Bit 1/Transmit HDLC Channel Select Bit 1 (THCS1). Select Channel 2, 10, 18, or 26. Bit 2/Transmit HDLC Channel Select Bit 2 (THCS2). Select Channel 3, 11, 19, or 27. Bit 3/Transmit HDLC Channel Select Bit 3 (THCS3). Select Channel 4, 12, 20, or 28. Bit 4/Transmit HDLC Channel Select Bit 4 (THCS4). Select Channel 5, 13, 21, or 29. Bit 5/Transmit HDLC Channel Select Bit 5 (THCS5). Select Channel 6, 14, 22, or 30. Bit 6/Transmit HDLC Channel Select Bit 6 (THCS6). Select Channel 7, 15, 23, or 31. Bit 7/Transmit HDLC Channel Select Bit 7 (THCS7). Select Channel 8, 16, 24, or 32.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TCB8SE 0 H1TTSBS, H2TTSBS HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select 9Bh, ABh 6 TCB7SE 0 5 TCB6SE 0 4 TCB5SE 0 3 TCB4SE 0 2 TCB3SE 0 1 TCB2SE 0 0 TCB1SE 0
Bit 0/Transmit Channel Bit 1 Suppress Enable/Sa8 Bit Enable (TCB1SE). LSB of the channel. Set to 1 to stop this bit from being used. Bit 1/Transmit Channel Bit 2 Suppress Enable/Sa7 Bit Enable (TCB1SE). Set to 1 to stop this bit from being used. Bit 2/Transmit Channel Bit 3 Suppress Enable/Sa6 Bit Enable (TCB1SE). Set to 1 to stop this bit from being used. Bit 3/Transmit Channel Bit 4 Suppress Enable/Sa5 Bit Enable (TCB1SE). Set to 1 to stop this bit from being used. Bit 4/Transmit Channel Bit 5 Suppress Enable/Sa4 Bit Enable (TCB1SE). Set to 1 to stop this bit from being used. Bit 5/Transmit Channel Bit 6 Suppress Enable (TCB1SE). Set to 1 to stop this bit from being used. Bit 6/Transmit Channel Bit 7 Suppress Enable (TCB1SE). Set to 1 to stop this bit from being used. Bit 7/Transmit Channel Bit 8 Suppress Enable (TCB1SE). MSB of the channel. Set to 1 to stop this bit from being used.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 SR6, SR7 HDLC #1 Status Register 6 HDLC #2 Status Register 7 20h, 22h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0
Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the transmit 128-byte FIFO has at least 1 byte available. Bit 1/Transmit FIFO Below Low-Watermark Condition (TLWM). Set when the transmit 128-byte FIFO empties beyond the low watermark as defined by the transmit low-watermark register (TLWMR). Bit 2/Receive FIFO Not Empty Condition (RNE). Set when the receive 128-byte FIFO has at least 1 byte available for a read. Bit 3/Receive FIFO Above High-Watermark Condition (RHWM). Set when the receive 128-byte FIFO fills beyond the high watermark as defined by the receive high-watermark register (RHWMR). Bit 4/Receive Packet-Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a latched bit and is cleared when read. Bit 5/Receive Packet-End Event (RPE). Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and is cleared when read. Bit 6/Transmit Message-End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. This is a latched bit and is cleared when read.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 IMR6, IMR7 HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 21h, 23h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0
Bit 0/Transmit FIFO Not Full Condition (TNF) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 1/Transmit FIFO Below Low-Watermark Condition (TLWM) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 2/Receive FIFO Not Empty Condition (RNE) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 3/Receive FIFO Above High-Watermark Condition (RHWM) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising edge only Bit 4/Receive Packet-Start Event (RPS) 0 = interrupt masked 1 = interrupt enabled Bit 5/Receive Packet-End Event (RPE) 0 = interrupt masked 1 = interrupt enabled Bit 6/Transmit Message-End Event (TMEND) 0 = interrupt masked 1 = interrupt enabled
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 INFO5, INFO6 HDLC #1 Information Register HDLC #2 Information Register 2Eh, 2Fh 6 -- 0 5 TEMPTY 0 4 TFULL 0 3 REMPTY 0 2 PS2 0 1 PS1 0 0 PS0 0
Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 0 0 0 0 1 PS1 0 0 1 1 0 PS0 0 1 0 1 0 In Progress Packet OK: Packet ended with correct CRC codeword CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword Abort: Packet ended because an abort signal was detected (seven or more 1s in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full. Packet Status
Bit 3/Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty. Bit 4/Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full. Bit 5/Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 INFO4 HDLC Event Information Register #4 2Dh 6 -- 0 5 -- 0 4 -- 0 3 H2UDR 0 2 H2OBT 0 1 H1UDR 0 0 H1OBT 0
Bit 0/HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 1/HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read. Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read.
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22.3.3 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer.
Register Name: Register Description: Register Address: Bit # Name Default 7 TFBA7 0 H1TFBA, H2TFBA HDLC # 1 Transmit FIFO Buffer Available HDLC # 2 Transmit FIFO Buffer Available 9Fh, Afh 6 TFBA6 0 5 TFBA5 0 4 TFBA4 0 3 TFBA3 0 2 TFBA2 0 1 TFBA1 0 0 TFBA0 0
Bits 0 to 7/Transmit FIFO Bytes Available (TFBAO to TFBA7). TFBA0 is the LSB.
22.3.4 Receive Packet-Bytes Available The lower 7 bits of the receive packet-bytes available register indicates the number of bytes (0 through 127) that can be read from the receive FIFO. The value indicated by this register (lower seven bits) informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value refers to one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register, the host then checks the HDLC information register for detailed message status. If the value in the HxRPBA register refers to the beginning portion of a message or continuation of a message, then the MSB of the HxRPBA register returns a value of 1. This indicates that the host can safely read the number of bytes returned by the lower seven bits of the HxRPBA register, but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise).
Register Name: Register Description: Register Address: Bit # Name Default 7 MS 0 H1RPBA, H2RPBA HDLC # 1 Receive Packet Bytes Available HDLC # 2 Receive Packet Bytes Available 9Ch, ACh 6 RPBA6 0 5 RPBA5 0 4 RPBA4 0 3 RPBA3 0 2 RPBA2 0 1 RPBA1 0 0 RPBA0 0
Bits 0 to 6/Receive FIFO Packet Bytes Available Count (RPBA0 to RPBA6). RPBA0 is the LSB. Bit 7/Message Status (MS) 0 = bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the INFO5 or INFO6 register for details. 1 = bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the INFO5 or INFO6 register.
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22.3.5
HDLC FIFOs
H1TF, H2TF HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO 9Dh, ADh 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0
Register Name: Register Description: Register Address: Bit # Name Default 7 THD7 0
Bit 0/Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte. Bit 1/Transmit HDLC Data Bit 1 (THD1) Bit 2/Transmit HDLC Data Bit 2 (THD2) Bit 3/Transmit HDLC Data Bit 3 (THD3) Bit 4/Transmit HDLC Data Bit 4 (THD4) Bit 5/Transmit HDLC Data Bit 5 (THD5) Bit 6/Transmit HDLC Data Bit 6 (THD6) Bit 7/Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte. Register Name: Register Description: Register Address: Bit # Name Default 7 RHD7 0 H1RF, H2RF HDLC # 1 Receive FIFO HDLC # 2 Receive FIFO 9Eh, AEh 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0
Bit 0/Receive HDLC Data Bit 0 (RHD0). LSB of an HDLC packet data byte. Bit 1/Receive HDLC Data Bit 1 (RHD1) Bit 2/Receive HDLC Data Bit 2 (RHD2) Bit 3/Receive HDLC Data Bit 3 (RHD3) Bit 4/Receive HDLC Data Bit 4 (RHD4) Bit 5/Receive HDLC Data Bit 5 (RHD5) Bit 6/Receive HDLC Data Bit 6 (RHD6) Bit 7/Receive HDLC Data Bit 7 (RHD7). MSB of an HDLC packet data byte. 145 of 262
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22.4 Receive HDLC Code Example
The following is an example of a receive HDLC routine:
1) Reset receive HDLC controller. 2) Set HDLC mode, mapping, and high watermark. 3) Start new message buffer. 4) Enable RPE and RHWM interrupts. 5) Wait for interrupt. 6) Disable RPE and RHWM interrupts. 7) Read HxRPBA register. N = HxRPBA (lower 7 bits are byte count, MSB is status). 8) Read (N and 7Fh) bytes from receive FIFO and store in message buffer. 9) Read INFO5 register. 10) If PS2, PS1, PS0 = 000, then go to Step 4. 11) If PS2, PS1, PS0 = 001, then packet terminated OK, save present message buffer. 12) If PS2, PS1, PS0 = 010, then packet terminated with CRC error. 13) If PS2, PS1, PS0 = 011, then packet aborted. 14) If PS2, PS1, PS0 = 100, then FIFO overflowed. 15) Go to Step 3.
22.5 Legacy FDL Support (T1 Mode)
22.5.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the DS2156 maintains the circuitry that existed in the previous generation of the T1 framer. In new applications, it is recommended that the HDLC controllers and BOC controller described in Section 20 and 22 are used. 22.5.2 Receive Section In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register (RFDL). Because the RFDL is 8 bits in length, it fills up every 2ms (8 x 250s). The framer signals an external microcontroller that the buffer has filled through the SR8.3 bit. If enabled through IMR8.3, the INT pin toggles low, indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the RFDLM1 or RFDLM2 registers, then the SR8.1 bit is set to a 1 and the INT pin toggles low if enabled through IMR8.1. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event occurs. The framer also contains a zero destuffer, which is controlled through the T1RCR2.3 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of an LAPD protocol. The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled through T1RCR2.3, the DS2156 automatically looks for five 1s in a row, followed by a 0. If it finds such a pattern, it automatically removes the zero. If the zero destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The T1RCR2.3 bit should always be set to a 1 when the DS2156 is extracting the FDL. Refer to Application Note 335: DS2141A, DS2151 Controlling the FDL for information about using the DS2156 in FDL applications in this legacy support mode.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RFDL7 0 RFDL Receive FDL Register C0h 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0
The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. Bit 0/Receive FDL Bit 0 (RFDL0). LSB of the received FDL code. Bit 1/Receive FDL Bit 1 (RFDL1) Bit 2/Receive FDL Bit 2 (RFDL2) Bit 3/Receive FDL Bit 3 (RFDL3) Bit 4/Receive FDL Bit 4 (RFDL4) Bit 5/Receive FDL Bit 5 (RFDL5) Bit 6/Receive FDL Bit 6 (RFDL6) Bit 7/Receive FDL Bit 7 (RFDL7). MSB of the received FDL code. Register Name: Register Description: Register Address: Bit # Name Default
7 RFDLM7 0
RFDLM1, RFDLM2 Receive FDL Match Register 1 Receive FDL Match Register 2 C2h, C3h
6 RFDLM6 0 5 RFDLM5 0 4 RFDLM4 0 3 RFDLM3 0 2 RFDLM2 0 1 RFDLM1 0 0 RFDLM0 0
Bit 0/Receive FDL Match Bit 0 (RFDLM0). LSB of the FDL match code. Bit 1/Receive FDL Match Bit 1 (RFDLM1) Bit 2/Receive FDL Match Bit 2 (RFDLM2) Bit 3/Receive FDL Match Bit 3 (RFDLM3) Bit 4/Receive FDL Match Bit 4 (RFDLM4) Bit 5/Receive FDL Match Bit 5 (RFDLM5) Bit 6/Receive FDL Match Bit 6 (RFDLM6) Bit 7/Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL match code.
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22.5.3 Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new value is written to the TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits have been shifted out, the framer signals the host microcontroller by setting the SR8.2 bit to a 1 that the buffer is empty and that more data is needed. The INT also toggles low if enabled through IMR8.2. The user has 2ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL is transmitted once again. The framer also contains a zero stuffer that is controlled through the T1TCR2.5 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of an LAPD protocol. The LAPD protocol states that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled through T1TCR2.5, the framer automatically looks for five 1s in a row. If it finds such a pattern, it automatically inserts a 0 after the five 1s. The T1TCR2.5 bit should always be set to a 1 when the framer is inserting the FDL.
Register Name: Register Description: Register Address: Bit # Name Default 7 TFDL7 0 TFDL Transmit FDL Register C1h 6 TFDL6 0 5 TFDL5 0 4 TFDL4 0 3 TFDL3 0 2 TFDL2 0 1 TFDL1 0 0 TFDL0 0
Note: Also used to insert Fs framing pattern in D4 framing mode.
The transmit FDL register (TFDL) contains the FDL information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. Bit 0/Transmit FDL Bit 0 (TFDL0). LSB of the transmit FDL code. Bit 1/Transmit FDL Bit 1 (TFDL1) Bit 2/Transmit FDL Bit 2 (TFDL2) Bit 3/Transmit FDL Bit 3 (TFDL3) Bit 4/Transmit FDL Bit 4 (TFDL4) Bit 5/Transmit FDL Bit 5 (TFDL5) Bit 6/Transmit FDL Bit 6 (TFDL6) Bit 7/Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code.
22.6 D4/SLC-96 Operation
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the device to properly insert the Fs framing pattern, the TFDL register at address C1h must be programmed to 1Ch and the following bits must be programmed as shown:
T1TCR1.2 = 0 (source Fs data from the TFDL register) T1TCR2.6 = 1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields through the TFDL and RFDL registers. Refer to Application Note 345: DS2141A, DS2151, DS2152 SLC96 for a detailed description about implementing an SLC-96 function.
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23.
LINE INTERFACE UNIT (LIU)
The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1-LIC4), which are described in the following sections. The LIU has its own T1/E1 mode-select bit and can operate independently of the framer function. The DS2156 can switch between T1 or E1 networks without changing any external components on either the transmit or receive side. Figure 23-3 shows a network connection using minimal components. In this configuration, the DS2156 can connect to T1, J1, or E1 (75 or 120) without any component change. The receiver can adjust the 120 termination to 100 or 75. The transmitter can adjust its output impedance to provide high return-loss characteristics for 120, 100, and 75 lines. Other components can be added to this configuration to meet safety and network protection requirements (Section 23.8).
23.1 LIU Operation
The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer-coupled into the RTIP and RRING pins of the DS2156. The user has the option to use internal termination, software selectable for 75/100/120 applications, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter-attenuation mux outputting the received line clock at RCLKO and bipolar or NRZ data at RPOSO and RNEGO. The DS2156 contains an active filter that reconstructs the analog-received signal for the nonlinear losses that occur in transmission. The receive circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allow the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOSI and TNEGI is sent through the jitter-attenuation mux to the waveshaping circuitry and line driver. The DS2156 drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1.
23.2 Receiver
The DS2156 contains a digital clock recovery system. The DS2156 couples to the receive E1 or T1 twisted pair (or coaxial cable in 75 E1 applications) through a 1:1 transformer. See Table 23-A for transformer details. The DS2156 has the option of using software-selectable termination requiring only a single fixed pair of termination resistors. The DS2156's LIU is designed to be fully software selectable for E1 and T1, requiring no change to any external resistors for the receive side. The receive side allows the user to configure the DS2156 for 75, 100, or 120 receive termination by setting the RT1 (LIC4.1) and RT0 (LIC4.0) bits. When using the internal termination feature, the resistors labeled R in Figure 23-3 should be 60 each. If external termination is used, RT1 and RT0 should be set to 0 and the resistors labeled R in Figure 23-3 should be 37.5, 50, or 60 each, depending on the line impedance. There are two ranges of user-selectable receive sensitivity for T1 and E1. The EGL bit of LIC1 (LIC1.4) selects the full or limited sensitivity. The resultant E1 or T1 clock derived from MCLK is multiplied by 16 through an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16-times over-sampler that is used to recover the clock and data. This over-sampling technique offers outstanding performance to meet jitter tolerance specifications shown in Figure 23-7.
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Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter high cycles of the clock. This is because of the highly oversampled digital-clock recovery circuitry. See the Receive AC Timing Characteristics in Section 36.3 for more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs and the RCLK is derived from the JACLK source. 23.2.1 Receive Level Indicator and Threshold Interrupt The DS2156 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3-RL0 located in Information Register 2 (INFO2). This feature is helpful when trouble-shooting lineperformance problems. The DS2156 can initiate an interrupt whenever the input falls below a certain level through the input-level under-threshold indicator (SR1.7). Using the RLT0-RLT4 bits of the CCR4 register, the user can set a threshold in 2.5dB increments. The SR1.7 bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in RLT0-RLT4. The level must remain below the programmed threshold for approximately 50ms for this bit to be set. 23.2.2 Receive G.703 Synchronization Signal (E1 Mode) The DS2156 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703, October 1998. In order to use the DS2156 in this mode, set the receive synchronization clock enable (LIC3.2) = 1. 23.2.3 Monitor Mode Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry. The DS2156 can be programmed to support these applications through the monitor mode control bits MM1 and MM0 in the LIC3 register (Figure 23-1).
Figure 23-1. Typical Monitor Application
T1/E1 LINE
PRIMARY T1/E1 TERMINATING DEVICE Rm
X F M R
Rm
Rt
DS2156
MONITOR PORT JACK
SECONDARY T1/E1 TERMINATING DEVICE
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23.3 Transmitter
The DS2156 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the DS2156 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user selects which waveform is generated by setting the ETS bit (LIC2.7) for E1 or T1 operation, then programming the L2/L1/L0 bits in register LIC1 for the appropriate application. A 2.048MHz or 1.544MHz clock is required at TCLKI for transmitting data presented at TPOSI and TNEGI. Normally these pins are connected to TCLKO, TPOSO, and TNEGO. However, the LIU can operate in an independent fashion. ITU specification G.703 requires an accuracy of 50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of 32ppm for T1 interfaces. The clock can be sourced internally from RCLK or JACLK. See LIC2.3, LIC4.4, and LIC4.5 for details. Because of the nature of the transmitter's design, very little jitter (less than 0.005UIP-P broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of TCLK. The transmitter in the DS2156 couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1 applications) through a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used must meet the specifications listed in Table 23-A. The DS2156 has the option of using software-selectable transmit termination. 23.3.1 Transmit Short-Circuit Detector/Limiter The DS2156 has an automatic short-circuit limiter that limits the source current to 50mA (RMS) into a 1 load. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (INFO2.5) provides a real-time indication of when the current limiter is activated. If the current limiter is disabled, TCLE indicates that a short-circuit condition exists. Status Register SR1.2 provides a latched version of the information, which can be used to activate an interrupt when enabled by the IMR1 register. The TPD bit (LIC1.0) powers down the transmit line driver and three-states the TTIP and TRING pins. 23.3.2 Transmit Open-Circuit Detector The DS2156 can also detect when the TTIP or TRING outputs are open circuited. TOCD (INFO2.4) provides a real-time indication of when an open circuit is detected. SR1 provides a latched version of the information (SR1.1), which can be used to activate an interrupt when enabled by the IMR1 register. 23.3.3 Transmit BPV Error Insertion When IBPV (LIC2.5) is transitioned from a 0 to a 1, the device waits for the next occurrence of three consecutive 1s to insert a BPV. IBPV must be cleared and set again for another BPV error insertion. 23.3.4 Transmit G.703 Synchronization Signal (E1 Mode) The DS2156 can transmit the 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703, October 1998. In order to transmit the 2.048MHz clock, when in E1 mode, set the transmit synchronization clock enable (LIC3.1) = 1.
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23.4 MCLK Prescaler
A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of 50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of 32ppm for T1 interfaces. A prescaler divides the 16MHz, 8MHz, or 4MHz clock down to 2.048MHz. There is an on-board PLL for the jitter attenuator, which converts the 2.048MHz clock to a 1.544MHz rate for T1 applications. Setting JAMUX (LIC2.3) to a logic 0 bypasses this PLL.
23.5 Jitter Attenuator
The DS2156 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits through the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in Figure 23-9. The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit (LIC1.3). Setting the DJA bit (LIC1.1) disables (in effect, removes) the jitter attenuator. On-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the DS2156 divides the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (JALT) bit in Status Register 1 (SR1.4).
23.6 CMI (Code Mark Inversion) Option
The DS2156 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B signal type. Ones are encoded as either a logical 1 or 0 level for the full duration of the clock period. Zeros are encoded as a 0-to-1 transition at the middle of the clock period.
Figure 23-2. CMI Coding
CLOCK DATA CMI
1
1
0
1
0
0
1
Transmit and receive CMI are enabled through LIC4.7. When this register bit is set, the TTIP pin outputs CMI-coded data at normal levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the user can also use HDB3/B8ZS coding. When this register bit is set, the RTIP pin becomes a unipolar CMI input. The CMI signal is processed to extract and align the clock with data.
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23.7 LIU Control Registers
Register Name: Register Description: Register Address: Bit # Name Default 7 L2 0 LIC1 Line Interface Control 1 78h 6 L1 0 5 L0 0 4 EGL 0 3 JAS 0 2 JABDS 0 1 DJA 0 0 TPD 0
Bit 0/Transmit Power-Down (TPD) 0 = powers down the transmitter and three-states the TTIP and TRING pins 1 = normal transmitter operation Bit 1/Disable Jitter Attenuator (DJA) 0 = jitter attenuator enabled 1 = jitter attenuator disabled Bit 2/Jitter Attenuator Buffer Depth Select (JABDS) 0 = 128 bits 1 = 32 bits (use for delay-sensitive applications) Bit 3/Jitter Attenuator Select (JAS) 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Bit 4/Receive Equalizer Gain Limit (EGL). This bit controls the sensitivity of the receive equalizer. T1 Mode 0 = -36dB (long haul) 1 = 15dB (limited long haul) E1 Mode 0 = -10dB (short haul) 1 = -43dB (long haul) Bits 5 to 7/Line Buildout Select (L0 to L2). When using the internal termination, the user needs only to select 000 for 75 operation or 001 for 120 operation below. This selects the proper voltage levels for 75 or 120 operation. Using TT0 and TT1 of the LICR4 register, the user can then select the proper internal source termination. Line buildouts 100 and 101 are for backwards compatibility with older products only. E1 Mode L2 0 0 1 1 L1 0 0 0 0 L0 0 1 0 1 Application 75 normal 120 normal 75 with high return loss* 120 with high return loss* N (1) 1:2 1:2 1:2 1:2 Return Loss NM NM 21dB 21dB Rt (1) () 0 0 6.2 11.6
*TT0 and TT1 of LIC4 register must be set to 0 in this configuration.
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DS2156 T1 Mode L2 L1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
L0 0 1 0 1 0 1 0 1
Application DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft) DSX-1 (266ft to 399ft) DSX-1 (399ft to 533ft) DSX-1 (533ft to 655ft) -7.5dB CSU -15dB CSU -22.5dB CSU
N (1) 1:2 1:2 1:2 1:2 1:2 1:2 1:2 1:2
Return Loss NM NM NM NM NM NM NM NM
Rt (1) () 0 0 0 0 0 0 0 0
Register Name: Register Description: Register Address: Bit # Name Default 7 ETS 0
LIC2 Line Interface Control 2 79h 6 LIRST 0 5 IBPV 0 4 TUA1 0 3 JAMUX 0 2 -- 0 1 SCLD 0 0 CLDS 0
Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a 1 redefines the operation of the transmit line driver. When this bit is set to a 1 and LIC1.5 = LIC1.6 = LIC1.7 = 0, the device generates a square wave at the TTIP and TRING outputs instead of a normal waveform. When this bit is set to a 1 and LIC1.5 = LIC1.6 = LIC1.7 0, the device forces TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull operation. This bit should be set to 0 for normal operation of the device. Bit 1/Short-Circuit Limit Disable (ETS = 1) (SCLD). Controls the 50mA (RMS) current limiter. 0 = enable 50mA current limiter 1 = disable 50mA current limiter Bit 2/Unused, must be set to 0 for proper operation Bit 3/Jitter Attenuator Mux (JAMUX). Controls the source for JACLK. 0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK) 1 = JACLK sourced from internal PLL (2.048MHz at MCLK) Bit 4/Transmit Unframed All Ones (TUA1). The polarity of this bit is set such that the device transmits an allones pattern on power-up or device reset. This bit must be set to a 1 to allow the device to transmit data. The transmission of this data pattern is always timed off of the JACLK. 0 = transmit all ones at TTIP and TRING 1 = transmit data normally Bit 5/Insert BPV (IBPV). A 0-to-1 transition on this bit causes a single BPV to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive 1s to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 6/Line Interface Reset (LIRST). Setting this bit from a 0 to a 1 initiates an internal reset that resets the clock recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Bit 7/E1/T1 Select (ETS) 0 = T1 mode selected 1 = E1 mode selected 154 of 262
DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 LIC3 Line Interface Control 3 7Ah 6 TCES 0 5 RCES 0 4 MM1 0 3 MM0 0 2 RSCLKE 0 1 TSCLKE 0 0 TAOZ 0
Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a ...101010... pattern (customer disconnect indication signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK. 0 = disabled 1 = enabled Bit 1/Transmit Synchronization G.703 Clock Enable (TSCLKE) 0 = disable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock 1 = enable 1.544MHz (T1)/2.048MHz (E1) transmit synchronization clock Bit 2/Receive Synchronization G.703 Clock Enable (RSCLKE) 0 = disable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode 1 = enable 1.544MHz (T1)/2.048MHz (E1) synchronization receive mode Bits 3 to 4/Monitor Mode (MM0 to MM1) MM1 0 0 1 1 MM0 0 1 0 1 Internal Linear Gain Boost (dB) Normal operation (no boost) 20 26 32
Bit 5/Receive-Clock Edge Select (RCES). Selects which RCLKO edge to update RPOSO and RNEGO. 0 = update RPOSO and RNEGO on rising edge of RCLKO 1 = update RPOSO and RNEGO on falling edge of RCLKO Bit 6/Transmit-Clock Edge Select (TCES). Selects which TCLKI edge to sample TPOSI and TNEGI. 0 = sample TPOSI and TNEGI on falling edge of TCLKI 1 = sample TPOSI and TNEGI on rising edge of TCLKI Bit 7/Unused, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 CMIE 0 LIC4 Line Interface Control 4 7Bh 6 CMII 0 5 MPS1 0 4 MPS0 0 3 TT1 0 2 TT0 0 1 RT1 0 0 RT0 0
Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 0 0 1 1 RT0 0 1 0 1 Internal Receive-Termination Configuration Internal receive-side termination disabled Internal receive-side 75 enabled Internal receive-side 100 enabled Internal receive-side 120 enabled
Bits 2, 3/Transmit Termination Select (TT0, TT1) TT1 0 0 1 1 TT0 0 1 0 1 Internal Transmit-Termination Configuration Internal transmit-side termination disabled Internal transmit -side 75 enabled Internal transmit -side 100 enabled Internal transmit -side 120 enabled
Bits 4, 5/MCLK Prescaler for T1 Mode MCLK (MHz) 1.544 3.088 6.176 12.352 2.048 4.096 8.192 16.384 MPS1 0 0 1 1 0 0 1 1 MPS0 0 1 0 1 0 1 0 1 JAMUX (LIC2.3) 0 0 0 0 1 1 1 1
Bits 4, 5/MCLK Prescaler for E1 Mode MCLK (MHz) 2.048 4.096 8.192 16.384 MPS1 0 0 1 1 MPS0 0 1 0 1 JAMUX (LIC2.3) 0 0 0 0
Bit 6/CMI Invert (CMII) 0 = CMI normal at TTIP and RTIP 1 = invert CMI signal at TTIP and RTIP Bit 7/CMI Enable (CMIE) 0 = disable CMI mode 1 = enable CMI mode 156 of 262
DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 BSYNC 0 INFO2 Information Register 2 11h 6 BD 0 5 TCLE 0 4 TOCD 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0
Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Receive Level (dB) Greater than -2.5 -2.5 to -5.0 -5.0 to -7.5 -7.5 to -10.0 -10.0 to -12.5 -12.5 to -15.0 -15.0 to -17.5 -17.5 to -20.0 -20.0 to -22.5 -22.5 to -25.0 -25.0 to -27.5 -27.5 to -30.0 -30.0 to -32.5 -32.5 to -35.0 -35.0 to -37.5 Less than -37.5
Bit 4/Transmit Open-Circuit Detect (TOCD). A real-time bit that is set when the device detects that the TTIP and TRING outputs are open-circuited. Bit 5/Transmit Current-Limit Exceeded (TCLE). A real-time bit that is set when the 50mA (RMS) current limiter is activated, whether the current limiter is enabled or not. Bit 6/BOC Detected (BD). A real-time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is currently being detected. Bit 7/BERT Real-Time Synchronization Status (BSYNC). Real-time status of the synchronizer (this bit is not latched). This bit is set when the incoming pattern matches for 32 consecutive bit positions. It is cleared when six or more bits out of 64 are received in error. Refer to BSYNC in the BERT status register, SR9, for an interruptgenerating version of this signal.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 SR1 Status Register 1 16h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0
Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is a double interrupt bit (Section 6.2). Bit 1/Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited. This is a double interrupt bit (Section 6.2). Bit 2/Transmit Current-Limit Exceeded Condition (TCLE). Set when the 50mA (RMS) current limiter is activated, whether the current limiter is enabled or not. This is a double interrupt bit (Section 6.2). Bit 3/Line Interface Receive Carrier-Loss Condition (LRCL). Set when the carrier signal is lost. This is a double interrupt bit (Section 6.2). Bit 4/Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful limit. This bit is cleared when read. Useful for debugging jitter attenuation operation. Bit 5/Receive Signaling Change-of-State Event (RSCOS). Set when any channel selected by the receive signaling change-of-state interrupt-enable registers (RSCSE1 through RSCSE4) changes signaling state. Bit 6/Timer Event (TIMER). Follows the error-counter update interval as determined by the ECUS bit in the error-counter configuration register (ERCNT). T1: set on increments of 1 second or 42ms based on RCLK E1: set on increments of 1 second or 62.5ms based on RCLK Bit 7/Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in CCR4.4 through CCR4.7. The level must remain below the programmed threshold for approximately 50ms for this bit to be set. This is a double interrupt bit (Section 6.2).
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 IMR1 Interrupt Mask Register 1 17h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0
Bit 0/Loss-of-Transmit Clock Condition (LOLITC) 0 = interrupt masked 1 = interrupt enabled--generates interrupts on rising and falling edges Bit 1/Transmit Open-Circuit Detect Condition (TOCD) 0 = interrupt masked 1 = interrupt enabled--generates interrupts on rising and falling edges Bit 2/Transmit Current-Limit Exceeded Condition (TCLE) 0 = interrupt masked 1 = interrupt enabled--generates interrupts on rising and falling edges Bit 3/Line Interface Receive Carrier-Loss Condition (LRCL) 0 = interrupt masked 1 = interrupt enabled--generates interrupts on rising and falling edges Bit 4/Jitter Attenuator Limit Trip Event (JALT) 0 = interrupt masked 1 = interrupt enabled Bit 5/Receive Signaling Change-of-State Event (RSCOS) 0 = interrupt masked 1 = interrupt enabled Bit 6/Timer Event (TIMER) 0 = interrupt masked 1 = interrupt enabled Bit 7/Input Level Under Threshold (ILUT) 0 = interrupt masked 1 = interrupt enabled
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23.8 Recommended Circuits Figure 23-3. Basic Interface
VDD
2:1
TRANSMIT LINE C
DS2156 TTIP DVDD DVSS TRING TVDD
0.1F 0.01F
0.1F
10F
1:1
RECEIVE LINE
+
0.1F 10F
RTIP
TVSS RVDD +
RRING RVSS R R
0.1F
Note 1: All resistor values are 1%. Note 2: Resistors R should be set to 60 each if the internal receive-side termination feature is enabled. When this feature is disabled, R = 37.5 for 75 coaxial E1 lines, 60 for 120 twisted-pair E1 lines, or 50 for 100 twisted-pair T1 lines. Note 3: C = 1F ceramic.
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Figure 23-4. Protected Interface Using Internal Receive Termination
VDD
D1 D2
VDD DS2156
TTIP DVDD DVSS 0.1F 0.01F
2:1
TRANSMIT LINE
F1 X2
S1
C1
0.1F D4 D3 TRING
TVDD TVSS
0.1F
F2
10F +
68F +
VDD
D5 D6 RTIP 0.1F D8
RVDD RVSS
0.1F 10F +
1:1
RECEIVE LINE
F3 X1
S2
RRING
F4
D7
60
60
0.1F
Note 1: All resistor values are 1%. Note 2: X1 and X2 are very low DCR transformers. Note 3: C1 = 1F ceramic. Note 4: S1 and S2 are 6V transient suppressers. Note 5: D1-D8 are Schottky diodes. Note 6: The optional fuses, F1-F4, prevent AC power line crosses from compromising the transformers. Note 7: The 68mF is used to keep the local power-plane potential within tolerance during a surge.
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23.9 Component Specifications Table 23-A. Transformer Specifications
SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) 2% 600mH (min) 1.0mH (max) 40pF (max) 1.0 (max) 2.0 (max) 1.2 (max) 1.2 (max)
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Figure 23-5. E1 Transmit Pulse Template
1.2 1.1
(IN 75 SYSTEMS, 1.0 ON THE SCALE = 2.37VPEAK IN 120 SYSTEMS, 1.0 ON THE SCALE = 3.00VPEAK) 269ns
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 TEMPLATE
TIME (ns)
Figure 23-6. T1 Transmit Pulse Template
1.2 1.1 1.0 0.9 0.8 0.7 NORMALIZED AMPLITUDE 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 T1.102/87, T1.403, CB 119 (OCT. 79), AND I.431 TEMPLATE
MAXIMUM CURVE UI Time Amp. -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 MINIMUM CURVE UI Time Amp. -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05
TIME (ns)
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Figure 23-7. Jitter Tolerance
1k DS2156 TOLERANCE TR 62411 (DEC. 90) 10 ITU-T G.823 1
UNIT INTERVALS (UIP-P)
100
0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k
Figure 23-8. Jitter Tolerance (E1 Mode)
1k DS2155 100
TOLERANCE
40
UNIT INTERVALS (UIP-P)
10
1.5
1
MINIMUM TOLERANCE LEVEL AS PER
ITU G.823 0.1 1
20 2.4k 18k
0.2
10
100 1k FREQUENCY (Hz)
10k
100k
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Figure 23-9. Jitter Attenuation (T1 Mode)
0dB
JITTER ATTENUATION (dB)
-20dB
e rv Cu A
-40dB
rve Cu B
TR 62411 (Dec. 90) Prohibited Area
DS2156 T1 MODE
-60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K
Figure 23-10. Jitter Attenuation (E1 Mode)
0dB
TBR12 Prohibited Area ITU G.7XX Prohibited Area
JITTER ATTENUATION (dB)
-20dB
-40dB
DS2156 E1 MODE
-60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K
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Figure 23-11. Optional Crystal Connections
DS2156 XTALD 1.544MHz/2.048MHz
MCLK C1 C2
Note 1: C1 and C2 should be 5pF lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS2156.
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24.
UTOPIA BACKPLANE INTERFACE
24.1 Description
The DS2156's UTOPIA interface maps the ATM cells in a T1/E1 frame in the transmit direction as per ATM Forum Specifications af-phy-0016.000 [1] and af-phy-0064.000 [2] and recovers them in the receive direction from a similar mapping. In the receive direction, the cell delineation mechanism used for finding ATM cell boundaries within a T1/E1 frame is performed as per ITU-T I.432 [4]. The terms "physical layer (PHY)" and "line side" are used synonymously in this document and refer to the device interface with the line side of the DS2156. The terms "ATM layer" and "system side" are used synonymously and refer to the UTOPIA-II interface of the DS2156. The transmit section receives cells from the ATM layer through the UTOPIA-II interface. It writes the cells into a 4-cell-deep transmit FIFO that is used for rate decoupling. The FIFO's depth is programmable to two, three, or four ATM cells. The cells are mapped into the T1/E1 frame as per [1] and [2]. The DS2156 can be configured to perform valid HEC insertion and payload scrambling. The receive section delineates the cells from the data received from the PHY layer as per [4]. Once cells are delineated, they are written into a 4-cell-deep receive FIFO used for rate decoupling. The receive section interfaces with the ATM layer through the UTOPIA-II interface. It can also be configured to perform payload descrambling and idle/unassigned cell filtering. Single-bit HEC error correction is also supported. 24.1.1 List of Applicable Standards 1) ATM Forum "DS1 Physical Layer Specification," af-phy-0016.000, September 1994 2) ATM Forum "E1 Physical Layer Specification," af-phy-0064.000, September 1996 3) ATM Forum "UTOPIA Level 2 Specification," Version 1.0, af-phy-0039.000, June 1995 4) B-ISDN User-Network Interface--Physical Layer Specification--ITU-T Recommendation I.432- 03/93 24.1.2 Acronyms and Definitions
DEFINITION Asynchronous Transfer Mode Cyclic Redundancy Check Header Error Check Loss-of-Cell Delineation Operations Administration and Maintenance Out-of-Loss Delineation Performance Monitoring Universal Test and Operations PHY Interface for ATM
ACRONYM ATM CRC HEC LCD OAM OCD PMON UTOPIA
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24.2 UTOPIA Clock Modes
When the UTOPIA backplane is enabled, the user can select from several clocking modes: full T1/E1, clear-channel E1, or fractional T1/E1. Because ATM bytes are byte-aligned in the frame, clear-channel mode is only available in E1 operation. See Table 24-A for the various register configurations. Figure 24-1 shows a simplified diagram of the clock, data, and sync connections between the framer and the UTOPIA block.
Figure 24-1. UTOPIA Clocking Configurations
CCR3.4 RCLK GAPPED CLOCK DATA NETWORK CCR3.5 TCLK GAPPED CLOCK DATA 1 0 SYNC DATA TCLK 1 0 CLOCK SYNC DATA UTOPIA BACKPLANE
RECEIVE FRAMER
FRAME SYNC
RECEIVE UTOPIA BLOCK
TRANSMIT FRAMER
CLOCK
FRAME SYNC
TRANSMIT UTOPIA BLOCK
24.3 Full T1/E1 Mode and Clear-Channel E1 Mode
In full T1/E1 mode, the framer is programmed to provide a constant clock (RCLK for the receiver and TCLK for the transmitter) to the UTOPIA block by setting CCR3.4 and CCR3.5 = 1. The framer also provides frame-sync pulses to the UTOPIA block. The UTOPIA block is programmed to use the clock and sync signals by setting U_TCR2.1 and U_RCR2.1 = 0. In this mode the UTOPIA block uses the sync signal to byte align the transmit data stream and locate the F-bit position in T1 operation and TS0 and TS16 in E1 operation. In T1 mode, the receive and transmit UTOPIA blocks always use the frame-sync pulse to gap out the Fbit position. In E1 mode, the transmit UTOPIA block can be programmed to gap out TS0 and TS16 by setting U_TCR1.3 = 0, or use the full 256 bits of the frame by setting U_TCR1.3 = 1. Using the full 256 bits of the frame is referred to as clear-channel mode and is only available in E1 mode. In full E1 mode, the receive UTOPIA block always uses the frame-sync pulse to gap out TS0 and TS16. In order for the receive UTOPIA block to operate in clear-channel mode, set U_RCR2.1 = 1 while in full clock mode or use the fractional mode of operation described in Section 24.4 with all channels selected.
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DS2156
24.4 Fractional T1/E1 mode
In fractional T1/E1 mode, the framer is programmed to provide a gapped clock by setting CCR3.4 and CCR3.5 = 0. The gapped clocks are synchronous with RCLK and TCLK. The UTOPIA block is programmed to use the clock and ignore the sync signals by setting U_TCR2.1 and U_RCR2.1 = 1. In this mode, the user can program the clock to be active during any time slot or group of time slots by using the transmit and receive fractional channel-select function in the per-channel pointer register (PCPR). See Section 5 for details on using this feature. In T1 mode, the F-bit is automatically gapped. In E1 mode, the user must program the clock to be gapped during TS0 and/or TS16 if desired.
Table 24-A. UTOPIA Clock Mode Configuration
MODE Full T1 mode, F-bit position gapped Full E1 mode, TS0 and TS16 gapped Full E1 mode, clearchannel (transmit) Full E1 mode, clearchannel (receive) Method #1 Full E1 mode, clearchannel (receive) Method #2 Fractional T1 mode U_TCFR.0 CCR3.4 U_RCFR.0 0 1 CCR3.5 1 U_TCR2.3 X U_TCR2.1 0 U_RCR2.1 0 COMMENTS Clear-channel operation is not available in T1 mode
1
1
1
0
0
0 Transmit framer must be set to TS0 pass-through mode E1TCR1.7 = 1 and transmit-signaling insertion disabled
1
--
1
1
0
0
1
1
--
X
--
1 Use PCPR and PCDR1-PCDR4 registers to make all receive channels active Use PCPR and PCDR1-PCDR4 registers to select active transmit and receive channels Use PCPR and PCDR1-PCDR4 registers to select active transmit and receive channels
1
0
--
X
--
1
0
0
0
X
1
1
Fractional E1 mode
1
0
0
X
1
1
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24.5 Transmit Operation
The DS2156 interface to the ATM layer is fully compliant to the ATM Forum's UTOPIA Level 2 specification [3]. Either direct status or multiplexed with 1CLAV mode is supported. The DS2156 can be configured to use any address, 0 to 3, as its UTOPIA port address, and uses a 4-cell buffer for cell-rate decoupling. The depth of the transmit FIFO is configurable to 2, 3, or 4 cells. When a port is polled and has cell space available, the DS2156 generates a cell available signal for that port. Additionally, the DS2156 generates a 2-cell space availability indication for each port. Note that this "2CLAV" indication follows the timing and polling cycles of UT-CLAV. Figure 24-2 shows the polling and cell transfer cycles for DS2156s used in a multiport configuration. Note that UT-SOC must be aligned with the first byte transfer. The DS2156 uses UT-SOC to detect the first byte of a cell. If a spurious UT-SOC comes during a cell transfer, then the DS2156 aligns with the latest UT-SOC and ignores the bytes (partial cell) received thus far. 24.5.1 UTOPIA Side Transmit: Muxed Mode with One Transmit CLAV
In the following functional description, a PHY is a single DS2156 and PHYs are multiple DS2156s.
In Level 2 UTOPIA, only one PHY at a time is selected for a cell transfer. However, another PHY can be polled for its UT-CLAV status while the selected PHY transfers data. The ATM layer polls the UTCLAV status of a PHY by placing its address on the transmit UTOPIA bus. The PHY drives UT-CLAV during each cycle following one with its address on the UT-ADDRx lines. The ATM layer selects a PHY for transfer by placing the port address of the PHY onto UT-ADDRx, when UT-ENB is deasserted during the current clock cycle, and asserted during the next clock cycle. All PHYs only examine the value on UT-ADDRx for selection purposes when UT-ENB is deasserted. The PHY is selected starting from the cycle after its address is on the UT-ADDRx lines and UT-ENB is deasserted. And ending in the cycle, another PHY is addressed for selection and UT-ENB is deasserted. Once a PHY is selected, the cell transfer is accomplished as described by the cell-level handshake of UTOPIA Level 1. To operate a PHY in a single PHY environment, the address pins should be set to the value programmed by the management interface. Figure 24-2 shows an example where PHYs are polled until the end of a cell transmission cycle. The UTCLAV signal shows that PHYs N - 3 and N + 3 can accept cells and PHY N + 3 is selected. The PHY is selected with the rising clock edge #16. Immediately after the beginning of cell transmission to PHY N + 3, the ATM layer starts polling again. Using the 2-clock polling cycles shown, up to 26 PHYs can be polled. This maximum value can only be reached if all responses occur in minimum delays, e.g., as shown, where, with clock edge #15, the response of the last PHY is obtained, immediately followed by the UT-ENB pulse to the PHYs. If an ATM implementation needs additional clock cycles to select the PHY, fewer than 26 PHY can be polled during one cell cycle. Note that if the ATM would decide to select PHY N again for the next cell transmission, it could leave the UT-ENB line asserted and start transmitting the next cell with clock edge #15. This results in a back-to-back cell transmission.
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Figure 24-2. Polling Phase and Selection Phase at Transmit Interface
SELECTION POLLING POLLING
UT-CLK UT-ADDRx UT-CLAV UT-ENB UT-DATAx UT-SOC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N+2
1F N+2
N-3
1F N-3
N-2
1F N-2
N-1
1F N-1
N+3
1F N+3
N+1
1F N+1
N
1F N
N+3
1F N+3
N+1
1F N+1
N-1
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
H1
H2
H3
H4
CELL XMIT TO:
PHY N
PHY N+3
Note that the active PHY (PHY N) is polled in octet P48. At this time, according to the UTOPIA Level 1 specification, the UT-CLAV signal of the PHY indicates the possibility of a subsequent cell transfer. Polling of PHY N before octet P44 would be possible but it does not indicate availability of the next cell.
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The example in Figure 24-3 shows where the transmission of cells though the transmit interface is stopped by the ATM, as no PHY is ready to accept cells. Polling continues. Several clock cycles later one PHY gets ready to accept a cell. During the transmission pause, the UT-DATAx and UT-SOC can go into high-impedance state as shown. UT-ENB is held in deasserted state. When a PHY is found that is ready to accept a cell (PHY_N + 3 in this case), the address of this PHY must be applied again to select it. This is necessary because of the 2-clock polling cycle, where the PHY is detected at the clock edge #15. At this time, the address of PHY N + 3 is no longer on the bus and therefore must be applied again in the next clock cycle. PHY N + 3 is selected with clock edge #16.
Figure 24-3. End and Restart of Cell at Transmit Interface
DETECTION POLLING
SELECTION POLLING
UT-CLK UT-ADDRx UT-CLAV
UT-ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N+1
1F
N
1F
N+3
1F
N+2
1F
N-1
1F
N
1F
N+3
1F N+3
N+3
1F N+3
N-2
1F
N-3
N+1
N
N+3
N+2
N-1
N
N-2
UT-DATAx UT-SOC
P45
P46
P47
P48
H1
H2
H3
H4
CELL XMIT TO:
PHY N
PHY N+3
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Figure 24-4 shows an example where the ATM must pause the data transmission, since it has no data available (in this case, for three clock cycles). This is done by deasserting UT-ENB and (optionally) setting UT-DATAx and UT-SOC into a high-impedance state. Polling can continue. In the last clock cycle before restarting the transmission, the address "M" of the previously selected PHY is put on the UT-ADDRx bus to reselect PHY M again.
Figure 24-4. Transmission to PHY Paused for Three Cycles
SELECTION POLLING POLLING
UT-CLK UT-ADDRx UT-CLAV
UT-ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
N
1F N
N+1
1F N+1
N-4
1F N-4
M
1F M
N+2
1F N+2
N+3
1F N+3
UT-DATAx UT-SOC
P31 P32 P33 P34
P35 P36 P37 P38 P39
CELL XMIT TO:
PHY M
PAUSE XMIT
PHY M
24.5.2 UTOPIA Side Transmit: Direct Status Mode (Multitransmit CLAV) The DS2156 supports direct status mode per [3] for a maximum of four PHY ports connected to one ATM layer. For each PHY port, the status signals UR-CLAV and UT-CLAV are permanently available according to UTOPIA Level 1 specification. PHY devices with up to four PHY ports on-chip have up to four UR-CLAV and up to four UT-CLAV status signals, one pair of UR-CLAV and UT-CLAV for each PHY port. Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. With respect to the status signals UR-CLAV and UT-CLAV, this mode of operation corresponds to that of four individual PHY devices according to UTOPIA Level 1. With respect to the cell transfer, this mode of operation corresponds to that as described in other parts of this document. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines (UR-ADDRx, UT-ADDRx), while the enable signal (UR-ENB, UT-ENB) is deasserted. All PHY ports examine only the value on the address lines for possible selection when the enable signal is deasserted. In case the ATM suspends transmission for a specific PHY port during a cell transfer, no cells to/from other PHY ports can be transferred during this time.
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Figure 24-5 shows an example of direct status for the transmit direction. Signals UT-CLAV[3:0] are associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device, thus "X = don't care" represents any address between 0 and 31 on the address lines UT-ADDRx or any data on the data bus. The polling of PHY ports starts while no cell transfer takes place. The ATM layer has pending cells for all four PHY ports (one individual queue for each PHY port) but all four PHY ports cannot accept a cell. With rising clock edge #2, PHY port #1 indicates that it can accept a complete cell (UT-CLAV0 asserted). The ATM layer detects this at clock edge #3. It selects that PHY port by placing address #1 on the address lines with rising clock edge #3. PHY port #1 detects this at clock edge #4. At clock edge #5, PHY port #1 detects UT-ENB asserted, therefore cell transfer for PHY port #1 starts with rising clock edge #5 (byte H1).
Figure 24-5. Example of Direct Status Indication, Transmit Direction
UT-CLK UT-ADDRx UT-CLAV(1) UT-CLAV(2) UT-CLAV(3) UT-CLAV(4)
UT-ENB
1
2
3
4
5
6
52
53
54
55
56
57
58
59
X PORT #1 PORT #2 PORT #3 PORT #4
1
X N-4
X = Don't Care
3
X
UT-SOC UT-DATAx X H1 H2 P44 P45 P46 P47 P48 Port #1 Transfer X H1 Port #3
At clock edge #5, the ATM layer detects a cell available at PHY port #3 (UT-CLAV2 asserted). With rising clock edge #52, PHY port #1 indicates that it cannot accept an additional cell by deasserting UTCLAV0. Thus, at clock edge #57, the ATM layer detects only UT-CLAV2 asserted (UT-CLAV1 and UTCLAV3 remain deasserted). The ATM layer deselects PHY port #1 and selects PHY port #3 for cell transfer with rising clock edge #57 by placing address #3 on the address lines and deasserting UT-ENB. PHY port #1 and PHY port #3 detect this at clock edge #58. At clock edge #59, PHY port #3 detects UT-ENB asserted, therefore cell transfer for PHY port #3 starts with rising clock edge #59 (byte H1). For additional examples, refer to [3].
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24.5.3 Transmit Processing The DS2156 can optionally insert a valid HEC byte in the cell header, or it can be programmed to transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55) addition can be optionally disabled. The generator polynomial used is 1 + X + X2 + X8. For idle/unassigned cell insertion (used for cell-rate decoupling), the DS2156 inserts a valid HEC byte with or without COSET addition, depending on the TCRDS bit (U_TCR1.3). The DS2156 can optionally scramble payload bytes, depending on the TPSE bit (U_TCR1.4) register bit. The polynomial used for scrambling is X43 + 1. For debugging purposes, the DS2156 can be configured to introduce a single-bit HEC error in the cell header of cells transmitted in a controlled manner. If configured in HEC errorinsertion mode, it inserts HEC errors in HEC ON PERIOD number of cells and turns off HEC error insertion for HEC OFF PERIOD number of cells set in the transmit HEC error-pattern register (U_THEPR). This process repeats periodically, until HEC error insertion is disabled through U_TCR1.1.
Figure 24-6. Transmit Cell Flow
UTOPIA II Data Input
Unassigned Cell Idle Cell
Transmit FIFO
Tx_Crd_sel
Tx_Coset_enb
HEC Insertion ON
HEC Insertion ON/OFF
HEC_insert_enb Tx_Coset_enb
Payload Scrambling ON/OFF
Scrambling_enb
HEC_OFF_period
HEC Error Insertion ON/OFF
HEC_err_insert_enb HEC_ON_period
Cell Data to Framer (PHY)
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24.6 Receive Operation
The receive interface of the DS2156 is fully compliant with the ATM Forum's UTOPIA Level 2 specifications [3]. The DS2156 can be configured to use any address in the range 0 to 31 as its UTOPIA port addresses. If the receive FIFO is not empty, the cell-available signal is asserted. After cell transfer from a port, the external cell-available signal updates based on the receive FIFO fill level only after oneclock cycle from cell-transfer completion. During this one-clock cycle, cell available indication for this port is kept in the deasserted state. One-clock minimum latency between two cell transfers from the same UTOPIA port is needed by the DS2156 to update its internal cell pointers. 24.6.1 Receive Processing The received bits, after ignoring framing overhead bits, are checked for possible HEC pattern. The polynomial used for HEC check is G(X) = 1 + X + X2 + X8, as recommended in [4]. The COSET subtraction (0x55) can be optionally disabled by clearing the register bit U_RCR1.0. The cell boundaries in the incoming bit stream are identified based on HEC. Figure 24-7 shows the celldelineation state machine. The cell-delineation state machine is initially in HUNT state. In HUNT state, it performs bit-by-bit hunting for correct HEC. If correct HEC is found, it transitions to the PRESYNC state where it cell-by-cell checks for correct HEC patterns. If DELTA consecutive correct patterns are received in PRESYNC, the cell-delineation state machine transits to SYNC state. Otherwise, it goes to HUNT state itself and starts bit-by-bit hunting. In SYNC state, if ALPHA consecutive incorrect HEC patterns are received, cell delineation is lost and it goes to HUNT state. In PRESYNC and SYNC states, only cell-bycell checking for proper HEC pattern is performed. ALPHA and DELTA are 7 and 6, respectively.
Figure 24-7. Cell-Delineation State Diagram
Bit by bit
HUNT
Correct HEC
ALPHA consecutive incorrect HEC
Incorrect HEC
PRESYNC
C ell by cell
SYNC
DELTA consecutive correct HEC
Cell by cell
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The persistence of an out-of-cell delineation (OCD) event is integrated into loss-of-cell delineation (LCD), based on programmable integration time period (receive LCD integration-period register). If OCD persists for the programmed time, LCD is declared. LCD is deasserted only when cell delineation persists in SYNC for the same programmed time. Whenever there is a change in LCD status, namely "into LCD" or "out of LCD," an external interrupt is optionally generated by the microprocessor interface based on the corresponding mask bit U_RCR2.4. The persistence is checked every system clock period divided by 16,383. The default value of receive LCD integration period register provides an integration time of 102ms in E1 mode and 135ms in T1 mode. If a single-bit header-error correction is enabled, the receiver mode of operation state machine follows the state machine given in Figure 24-8. Single-bit correction is done only if correction is enabled and the state machine is in "correction mode" of operation at the start-of-cell transfer. Receiver mode of operation is valid only when cell delineation is in SYNC state. 8-bit correctable and 12-bit uncorrectable HEC-errored cell counters are maintained as saturating counters.
Figure 24-8. Header Correction State Machine
Multi-bit error detected (cell discarded)
No error detected (no action)
Correction mode
No error detected (no action)
Detection mode
Error detected (cell discarded)
Single bit error detected (correction)
.
HEC error correction is accomplished based on the receiver mode of operation. In correction mode, only single-bit errors can be corrected and the receiver switches to detection mode. In detection mode, all cells with detected header errors are discarded, provided the U_RCR1.3 bit is set = 0. When a header is examined and found not to be in error, the receiver switches to correction mode. The term "no action" in Figure 24-8 means no correction is performed and no cell is discarded. The payload bytes of the cell are optionally descrambled using the self-synchronizing descrambler polynomial X43 + 1, as given in [4]. The descrambling can be enabled through the U_RCR1.2 bit. Descrambling is activated if cell delineation is in PRESYNC or SYNC state. The cell header is not affected by descrambling. After descrambling and single-bit header-error correction, the cells are written into the receive FIFO as long as cell delineation is in SYNC and the receive FIFO is not full. Idle and/or unassigned cells can be optionally filtered by properly programming the receive control register bits. Uncorrectable HEC-errored cells are normally filtered and are not written into the receive FIFO unless U_RCR1.3 is set. Note that if
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HEC error correction is disabled, all HEC-errored cells are termed as uncorrectable HEC-errored cells. A 16-bit count of the number of cells that can be written into receive FIFO is maintained, which saturates at FFFFh. Note that, whether or not ATM layer dequeues cells from the receive FIFO, this counter increments if valid cells are received. This counter is cleared by the microprocessor interface once it is latched. A 2k x 8 receive FIFO that holds 4-cell buffer space per port is maintained for rate decoupling. 24.6.2 UTOPIA Side Receive: Muxed Mode with One Receive CLAV The DS2156 drives the internal cell-available signals onto the external CLAV lines based on the configured polling mode. In direct status mode, only four ports are supported. If a port is conducting a cell transfer, its CLAV is kept asserted until the last byte is transferred to the ATM layer. This supports interfacing with the octet-level ATM layer also. Cell-available status for any fresh cell corresponding to a port has to be polled by the ATM layer only after the current cell transfer to the port is completed. The multiplexed bus with 1CLAV polling mode cycle is depicted in Figure 24-9 in which N, N + 2, N - 3, N 2, N - 1, N + 3, and N + 1 are considered part of DS2156 UTOPIA ports. During reception of a cell from PHY N, the other PHYs are polled. It turns out that PHY N - 3 and PHY N + 3 have cells available, and PHY N + 3 is ultimately selected. (Remember that the PHY number values are for example only). Just like the transmit interface, the 2-clock polling cycles allow up to 26 PHYs to be polled in the 8-bit mode.
Figure 24-9. Polling Phase and Selection at Receive Interface
SELECTION POLLING POLLING
UR-CLK UR-ADDRx UR-CLAV
UR_ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
N+2
1F N+2
N-3
1F N-3
N-2
1F N-2
N-1
1F N-1
N+3
1F N+3
N+1
1F N+1
N-1
1F N-1
N+3
1F N+3
N+1
1F N+1
N-1
UR-DATAx UR-SOC
P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48
H1
H2
H3
CELL RCV FROM:
PHY N
PHY N+3
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Figure 24-10 shows a case when, after the end of transmission of a cell from PHY N, no other PHY has a cell available. Therefore, UR-ENB remains asserted as the ATM assumes a cell-available from PHY N. With clock edge #9, it turns out that PHY N also has no cell available, as UR-SOC remains low. The ATM then deasserts UR-ENB while the polling of the PHYs continues. With clock edge #15, PHY N - 3 is found to have a cell for transmission. Thus, address N - 3 is applied and the PHY N - 3 is selected with clock edge #16. Additional receive interface examples are available in [3].
Figure 24-10. End and Restart of Cell Transmission at Receive Interface
DETECTION POLLING SELECTION POLLING
UR-CLK UR-ADDRx UR-CLAV
UR-ENB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
N-3
1F N-3
N+1
1F N+1
N-1
1F N-1
N
1F N
N+3
1F N+3
N-1
1F N-1
N-3
1F N-3
N-3
1F N-3
N+1
1F N+1
N+2
UR-DATAx UR-SOC
P42 P43 P44 P45 P46 P47 P48
XX
H1
H2
H3
CELL RCV FROM:
PHY N
PHY N-3
24.6.3 UTOPIA Side Receive: Direct Status Mode (Multireceive CLAV) Up to a maximum of four PHY ports can be connected to one ATM layer. For each PHY port, the status signals UR-CLAV and UT-CLAV are permanently available according to UTOPIA Level 1 specification. Status signals and cell transfers are independent of each other. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. With respect to the status signals UR-CLAV and UT-CLAV, this mode of operation corresponds to that of four individual PHY devices according to UTOPIA Level 1. With respect to the cell transfer, this mode of operation corresponds to that as described in this document and [3]. The ATM layer selects a PHY port for cell transfer by placing the desired port on the address lines (UR-ADDRx, UT-ADDRx), while the enable signal (UR-ENB, UT-ENB) is deasserted. All PHY ports only examine the value on the address lines for possible selection when the enable signal is deasserted. In case the ATM suspends transmission for a specific PHY port during a cell transfer, no cells to/from other PHY ports can be transferred during this time.
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An example for the receive direction is shown in Figure 24-11. The status signals UR-CLAVx are associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device so "X = don't care" on the address lines UR-ADDRx. In Figure 24-11, the polling of PHY ports starts while no cell transfer takes place. The ATM layer monitors all four status signals UR-CLAVx. At clock edge #3 it detects a cell available at PHY port #1, UR-CLAV(1) asserted. It selects that PHY port by placing address #1 on the address lines with rising clock edge #3. PHY port #1 detects this at clock edge #4. At clock edge #5, PHY port #1 detects UR-ENB asserted, thus cell transfer for PHY port #1 starts with rising clock edge #5. At clock edge #5 the ATM layer detects a cell available at PHY port #3, UR-CLAV(3) asserted. Not knowing whether PHY port #1 may have another cell available or not, the ATM layer deselects PHY port #1 and selects PHY port #3 for cell transfer with rising clock edge #57 by placing address #3 on the address lines and deasserting UR-ENB. PHY port #1 and PHY port #3 detect this at clock edge #58. At clock edge #59, PHY port #3 detects UR-ENB asserted, thus cell transfer starts with rising clock edge #59. At clock edge #111, no cell is available at PHY ports #1, #2, and #4. The ATM layer keeps UR-ENB asserted and detects at clock edge #113 the first byte of another cell available from PHY port #3, UR-CLAV(3) asserted. Thus, cell transfer takes place starting with rising clock edge #112. At clock edge #164, again, no cell is available at PHY ports #1, #2, and #4. The ATM layer keeps the UR-ENB asserted and also detects at clock edge #166 no cell available from PHY port #3, UR-CLAV(3) deasserted. Thus, the ATM layer deselects PHY port #3 by deasserting UR-ENB with rising clock edge #166.
Figure 24-11. Example of Direct Status Indication, Receive Direction
UR-CLK UR-ADDRx UR-CLAV(1) UR-CLAV(2) UR-CLAV(3) UR-CLAV(4)
UR-ENB
1
2
3
4
5
6
57
58
59
60
111
112
113
114
164
165
166
167
X PORT #1 PORT #2 PORT #3 PORT #4
1
X
3
X
X
X
UR-SOC UR-DATAx H1 P48 H1 P48 H1 H2 Cell Transfer (port #3) P48 X
Cell Transfer (port #1)
Cell Transfer (port #3)
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24.7 Register Definitions
The CCR2 register is used to configure the UTOPIA port address. The upper five bits of the CCR2 register contain the port address 0-31. The lower three bits are used for the backplane clock function. See Programmable Backplane Clock Synthesizer in Section 30.
Register Name: Register Description: Register Address: Bit # Name Default 7 TRPA4 0 CCR2 Common Control Register 2 71h 6 TRPA3 0 5 TRPA2 0 4 TRPA1 0 3 TRPA0 0 2 BPCS1 0 1 BPCS0 0 0 BPEN 0
Bit 0/BPEN. See Section 30 for more information. Bit 1/BPCS0. See Section 30 for more information. Bit 2/BPCS1. See Section 30 for more information. Bits 3 to 7/Transmit and Receive Port Address 0 to 4 (TRPA0 to TRPA4). The 5-bit value in this register is used to assign the UTOPIA interface 1 of 32 port addresses.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
U_TCFR UTOPIA Transmit Configuration Register 50h 6 -- 0 5 -- 0 4 -- 1 3 -- 0 2 -- 0 1 TPM 0 0 TPC 0
Bit 0/Transmit Port Configuration (TPC) 0 = T1 mode 1 = E1 mode Bit 1/Transmit Poll Mode (TPM). Transmit UTOPIA polling mode configuration 0 = multiplexed with 1CLAV mode 1 = direct status Bits 2 to 7/Unassigned, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 U_TPCL UTOPIA Transmit PMON Counter Latch Register 51h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0
Bits 0 to 7/The host should always write 0x00 to this register when latching the PMON counter. This register is provided for latching in the 16-bit transmit assigned cell-count value of a port into the common transmit assigned cell-counter latch register. For reading the transmit assigned cell-count value, software writes into this register and then reads from transmit-assigned cell-counter MSB and LSB registers. A write into this register clears the transmit-assigned cell-count value.
Register Name: Register Description: Register Address: Bit # Name Default 7 TACC15 0
U_TACC1 UTOPIA Transmit-Assigned Cell-Count Register 1 52h 6 TACC14 0 5 TACC13 0 4 TACC12 0 3 TACC11 0 2 TACC10 0 1 TACC9 0 0 TACC8 0
Bits 0 to 7/Transmit-Assigned Cell Count (TACC9 to TACC15) Register Name: Register Description: Register Address: Bit # Name Default 7 TACC7 0 U_TACC2 UTOPIA Transmit-Assigned Cell-Count Register 2 53h 6 TACC6 0 5 TACC5 0 4 TACC4 0 3 TACC3 0 2 TACC2 0 1 TACC1 0 0 TACC0 0
Bits 0 to 7/Transmit-Assigned Cell Count (TACC0 to TACC7) Transmit-assigned cell-count value reflects the number of ATM layer cells transmitted since last latching. For reading the 16-bit transmit-assigned cell count for a port, software has to write into the transmit PMON-counter latch-enable register for the port before reading these registers. Reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current MSB value.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TIUP7 0 U_TIUPB UTOPIA Transmit Idle/Unassigned Payload Byte Register 54h 6 TIUP6 1 5 TIUP5 1 4 TIUP4 0 3 TIUP3 1 2 TIUP2 0 1 TIUP1 1 0 TIUP0 0
Bits 0 to 7/Transmit Idle/Unassigned Payload (TIUP0 to TIUP7). Holds the payload byte to be carried in octets of idle/unassigned cells, transmitted towards line for cell rate decoupling.
Register Name: Register Description: Register Address: Bit # Name Default 7 HOFFP4 0
U_THEPR UTOPIA Transmit HEC Error-Insertion Pattern Register 55h 6 HOFFP3 0 5 HOFFP2 1 4 HOFFP1 0 3 HOFFP0 1 2 HONP2 0 1 HONP1 0 0 HONP0 1
Bits 0 to 2/HEC On Period (HONP0 to HONP2). Holds the number of cells in which incorrect HEC is sent if HEC error insertion is enabled. Bits 3 to 7/HEC Off Period (HOFFP0 to HOFFP4). Holds the number of cells in which correct HEC is sent if HEC error insertion is enabled. If HEC error insertion in the transmit control register is enabled for a port, then for the HEC off period cells are transmitted to the port with correct HEC. For the HEC on period, cells are sent with incorrect HEC. This cycle repeats until HEC error insertion is disabled. Note that HEC error is introduced in all transmitted cells based on the transmit HEC error-insertion pattern register, if the HEC error-insertion bit in the transmit control register is enabled irrespective of whether the HEC insertion bit in the transmit control register is enabled or disabled.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 U_TCR1 UTOPIA Transmit Control Register 1 56h 6 -- 0 5 -- 0 4 TPSE 0 3 TCRDS 0 2 TCAE 1 1 THEIE 0 0 THIE 1
Bit 0/Transmit HEC-Insertion Enable (THIE) 0 = HEC byte as received from ATM layer is transparently passed 1 = proper HEC value is computed and inserted in the HEC byte of the cell Bit 1/Transmit HEC Error-Insertion Enable (THEIE) 0 = HEC error insertion disabled 1 = HEC errors introduced in the transmitted cells as specified by transmit HEC error-insertion pattern register Bit 2/Transmit COSET-Addition Enable (TCAE) 0 = no COSET addition 1 = COSET (0x55) addition to the calculated HEC Note that if HEC insertion is disabled, then the HEC byte is transmitted transparently (this bit does not impact ATM layer cells). However, the HEC byte of idle/unassigned cells used for cell-rate decoupling includes COSET addition as long as the TCAE bit is enabled. Bit 3/Transmit Cell-Rate Decoupling Selection (TCRDS) 0 = idle cell 1 = unassigned cell Bit 4/Transmit Payload-Scrambling Enable (TPSE) 0 = disabling scrambling 1 = enabling scrambling Bits 5 to 7/Unassigned, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 U_TCR2 UTOPIA Transmit Control Register 2 57h 6 -- 0 5 FDC1 0 4 FDC0 0 3 TCES 0 2 -- 0 1 TPLIM 0 0 -- 0
Bits 0, 2, 6, 7/Unassigned, must be set to 0 for proper operation Bit 1/Transmit Physical-Layer Interface Mode (TPLIM) 0 = clock + data + frame-pulse indication combination 1 = gapped clock + data combination Bit 3/Transmit Clear E1 Selection (TCES). When this bit is set = 0, TS16 and TS0 are automatically gapped out. This is only meaningful when U_TCR2.1 is set = 0. E1TCR1.7 must be set = 1 if TCES = 1. 0 = TS16 and TS0 gapped out 1 = TS16 and TS0 not gapped out Bits 4, 5/Transmit FIFO Depth Configuration Bits (FDC1, FDC0) FDC1 0 0 1 1 FDC0 0 1 0 1 Cell Depth 4 3 2 Reserved
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
U_RCFR UTOPIA Receive Configuration Register 60h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 RUPM 0 0 RPC 0
Bit 0/Receive Port Configuration (RPC) 0 = T1 mode 1 = E1 mode Bit 1/Receive UTOPIA Polling Mode (RUPM) 0 = multiplexed with 1CLAV mode 1 = direct status Bits 2 to 7/Unassigned, should be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RLIP7 0 U_RLCDIP UTOPIA Receive LCD Integration Period Register 61h 6 RLIP6 1 5 RLIP5 1 4 RLIP4 0 3 RLIP3 0 2 RLIP2 1 1 RLIP1 1 0 RLIP0 0
Bits 0 to 7/Receive LCD Integration Period (RLIP0 to RLIP7) This 8-bit register holds the LCD integration period value for which the out-of-cell delineation condition must persist for declaring loss-of-cell delineation (LCD). For deasserting LCD, cell delineation should persist in the SYNC state for the same amount of time programmed in this register. LCD state change condition can be programmed to generate an external interrupt through U_RCR2.4. A value of 0 programmed into this register declares LCD for every OCD condition at the resolution of the internal system clock period. The internal system clock is 8x the line clock [16.383MHz (E1 mode) and 12.352MHz (T1 mode)]. IT = Integration Time in ms For E1 mode, register value = IT / 1ms For T1 mode, register value = IT / 1.326ms For example, in E1 mode a register value of 64h (100) generates a 100ms integration time. In T1 mode, a register value of 4Bh (75) generates a 100ms integration time.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
U_RPCE UTOPIA Receive PMON-Counter Enable Register 62h 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0 0 -- 0
Bits 0 to 7/The host should always write 0x00 to this register when latching the receive PMON counter. This register is provided for latching all receive PMON-counter values, namely the 16-bit receive assigned cellcount value, 12-bit receive uncorrectable HEC-count value, and 8-bit receive correctable HEC-count value of a port into the common receive assigned cell-counter latch register, receive uncorrectable HEC-counter latch register, and receive correctable HEC-count latch register, respectively. A write into this register clears the receive PMON counters for that port.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RCHC7 0 U_RCHEC UTOPIA Receive Correctable HEC Counter Register 63h 6 RCHC6 0 5 RCHC5 0 4 RCHC4 0 3 RCHC3 0 2 RCHC2 0 1 RCHC1 0 0 RCHC0 0
Bits 0 to 7/Receive Correctable HEC Counter (RCHC0 to RCHC7) Note that write access to the receive PMON-counter latch-enable register latches all receive PMON-counter values into temporary latch registers and clears the internal count values. This register holds the number of correctable HEC-errored cells received since last latching. Note that this count corresponds to cells received when cell delineation is in SYNC. A correctable HEC-errored cell is a cell with a single-bit error, provided single-bit HECerror correction is enabled through U_RCR1.1 and the receiver mode of operation is in correction mode. Correctable HEC count value is unaffected if HEC-error correction is disabled.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
U_RUHEC1 UTOPIA Receive Uncorrectable HEC Counter Register 1 64h 6 -- 0 5 -- 0 4 -- 0 3 RUHC11 0 2 RUHC10 0 1 RUHC9 0 0 RUHC8 0
Bits 0 to 3/Receive Uncorrectable HEC Counter (RUHC8 to RUHC11) Bits 4 to 7/Unused
Register Name: Register Description: Register Address: Bit # Name Default 7 RUHC7 0
U_RUHEC2 UTOPIA Receive Uncorrectable HEC Counter Register 2 65h 6 RUHC6 0 5 RUHC5 0 4 RUHC4 0 3 RUHC3 0 2 RUHC2 0 1 RUHC1 0 0 RUHC0 0
Bits 0 to 7/Receive Uncorrectable HEC Counter (RUHC0 to RUHC7) The U_RUHEC1 and U_RUHEC2 registers count the number of uncorrectable HEC-errored cells received since last latching. Note that this count corresponds to cells received when cell delineation is in SYNC. For every SYNCto-HUNT transition of the cell delineation state machine, the "Correctable + Uncorrectable" error-count value increases by 6 instead of 7. For every SYNC-to-HUNT transition, if HEC correction is enabled, the correctable HEC count increases by 1 and the uncorrectable HEC count increases by 5. If HEC correction is disabled, correctable HEC count is not affected and uncorrectable HEC count increases by 6. Note that cell delineation goes to HUNT state upon the reception of the 7th consecutive HEC pattern. Receive PMON counters are not updated when cell delineation is out of SYNC state. Note that write access to the receive PMON-counter latch-enable register latches internal receive PMON-counter values and clears them once they are latched. 187 of 262
DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 RACC15 0 U_RACC1 UTOPIA Receive-Assigned Cell Count Register 1 66h 6 RACC14 0 5 RACC13 0 4 RACC12 0 3 RACC11 0 2 RACC10 0 1 RACC9 0 0 RACC8 0
Bits0 to 7/Receive-Assigned Cell Count 8 to 15 (RACC8 to RACC15) Register Name: Register Description: Register Address: Bit # Name Default 7 RACC7 0 U_RACC2 UTOPIA Receive-Assigned Cell Count Register 2 67h 6 RACC6 0 5 RACC5 0 4 RACC4 0 3 RACC3 0 2 RACC2 0 1 RACC1 0 0 RACC0 0
Bits 0 to 7/Receive-Assigned Cell Count 0 to 7 (RACC0 to RACC7) The U_RACC1 and U_RACC2 registers are common registers for all ports. For software convenience, any of the eight addresses can be used to access these registers. For reading the 16-bit receive assigned cell count for a port, software has to write into the receive PMON-counter latch-enable register for the port before reading from these registers. Reading from these registers without writing into the latch-enable register returns the old value that was latched and not the current value of the receive-assigned cell count of a port. The assigned cell count value reflects the number of cells written into receive FIFO that can be read by the ATM layer since last latching. Note that whether or not the ATM layer dequeues cells from the receive FIFO, the assigned cell counter of a port is incremented upon the reception of a valid ATM layer cell when cell delineation is in SYNC state.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 U_RSR UTOPIA Receive Status Register 68h 6 -- 0 5 CDS1 0 4 CDS0 0 3 RMS 0 2 LCDS 1 1 LCDCSIS 0 0 FOIS 0
Bit 0/Receive FIFO Overrun Interrupt Status (FOIS). Set if the receive FIFO overruns provided RxFIFO overrun interrupt mask bit (U_RCR2.3) is set. This bit is reset when read. Bit 1/LCD Change-of-State Interrupt Status (LCDCSIS). Set by hardware if LCD status changes, provided that the LCD interrupt-mask bit (U_RCR2.4) is set. The LCDS bit indicates the current status of LCD. This bit is reset when read. Bit 2/LCD Status (LCDS) 0 = in-cell delineation 1 = loss-of-cell delineation Bit 3/Receiver Mode Status (RMS). This bit shows valid status only when HEC correction is enabled. 0 = correction mode 1 = detection mode Bits 4, 5/Cell Delineation Status 0 to 1 (CDS0 to CDS1). Bit 5 indicates instantaneous OCD status. CDS1 0 0 1 CDS0 0 1 x Cell Delineation Status HUNT State PRESYNC State SYNC State
Bits 6, 7/Unused Once a read cycle to this register is detected, the interrupt status bits are cleared. If any of the lower two bits is set, the external interrupt signal is asserted. If both the bits are 0 for all the ports, the external interrupt signal is deasserted.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 U_RCR1 UTOPIA Receive Control Register 1 69h 6 -- 0 5 RUCFE 0 4 RICFE 0 3 RPHEC 0 2 RDE 0 1 RHECE 0 0 RCSE 1
Bit 0/Receive COSET Subtraction Enable (RCSE) 0 = DS2156 does not do COSET subtraction from the HEC byte for checking HEC 1 = DS2156 subtracts COSET polynomial (0 x 55) from the HEC byte for checking HEC Bit 1/Receive HEC-Error Correction Enable (RHECE) 0 = single-bit HEC-error correction is disabled 1 = DS2156 corrects single-bit HEC errors based on the current state of receiver mode of operation. Singlebit error correction is done only if this bit is set and receiver mode of operation is in CORRECTION state. Bit 2/Receive Descrambling Enable (RDE) 0 = payload descrambling is disabled 1 = payload descrambling is enabled. Payload of cells received in PRESYNC and SYNC state of cell delineation are descrambled based on the self-synchronizing polynomial X43 + 1. Cell header is unaffected by descrambling. Bit 3/Receive Pass HEC-Errored Cells (RPHEC) 0 = DS2156 passes only error-free and error-corrected cells to ATM layer 1 = DS2156 passes all cells including HEC-errored cells, received when cell delineation is SYNC to ATM layer Bit 4/Receive Idle Cell-Filter Enable (RICFE) 0 = DS2156 does not filter idle cells 1 = DS2156 filters all idle cells received from being written into receive FIFO. The cell header of idle cell (first five bytes) is 0x00, 0x00, 0x00, 0x01 and proper HEC byte. Cell payload is not considered for idle cell filtering. Bit 5/Receive Unassigned Cell-Filter Enable (RUCFE) 0 = DS2156 will NOT filter unassigned cells. 1 = DS2156 filters all unassigned cells received from being written into receive FIFO. The cell header of unassigned cell (first five bytes) is 0x00, 0x00, 0x00, 0x00, and proper HEC byte. Cell payload is not considered for unassigned cell filtering Bits 6, 7/Unassigned, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 U_RCR2 UTOPIA Receive Control Register 2 6Ah 6 -- 0 5 -- 0 4 LCDIM 0 3 RFOIM 0 2 -- 0 1 RPLIM 0 0 DLBE 0
Bit 0/Diagnostic Loopback Enable (DLBE) 0 = normal operation 1 = diagnostic loopback is enabled. In this loopback, the transmit data and clock is looped back onto the receive side. Receiver uses transmit data and clock instead of receive data and clock from physical layer (typically framer). Bit 1/Receive Physical Layer Interface Mode (RPLIM) 0 = clock + data + frame pulse combination 1 = gapped clock + data combination Bit 2/Bit must be set = 1 after reset for proper UTOPIA bus mode operation Bit 3/Receive FIFO Overrun Interrupt Mask (RFOIM) 0 = DS2156 does not generate external interrupt for receive FIFO overrun events 1 = DS2156 generates external interrupt if receive FIFO overrun condition has occurred Bit 4/LCD Interrupt Mask (LCDIM) 0 = DS2156 does not generate external interrupt for LCD state changes 1 = DS2156 generates external interrupt if LCD state has changed Bits 5 to 7/Unassigned, must be set to 0 for proper operation
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24.8 Receive FIFO Overrun
Receive FIFO overrun condition indicates that receive FIFO has been written with four cells before ATM layer reads the cells. The four cells that cause receive FIFO overrun conditions are intact in receive FIFO, and subsequent cells are not written into receive FIFO until ATM layer reads a cell from receive FIFO for the port through UTOPIA-II interface. Receive FIFO overrun condition can optionally be made to raise external interrupt by setting receive FIFO overrun interrupt mask bit U_RCR2.3.
24.9 UTOPIA Diagnostic Loopback
Diagnostic loopback toward the ATM layer side (UTOPIA side) can be enabled through receive control register 2, U_RCR2.0. In diagnostic loopback, data, clock, and frame-pulse indication generated by the transmit section of the DS2156 are used instead of the corresponding signals from the physical layer device. Receive physical interface mode should be configured with the same value as transmit physical interface mode. Receive active-edge selection bit should be configured as the opposite edge of that used by the transmit section of the DS2156. It is possible to use the internally generated system clock divided by 8 in place of TCLK for this mode when enabled with U_TCR2.6.
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25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION
The DS2156 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TCD1 and TCD2) and selects the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register. When generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both transmit code-definition registers must be filled with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern is transmitted as long as the TLOOP control bit (T1CCR1.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer overwrites the repeating pattern once every 193 bits to send the F-bit position. For example, to transmit the standard "loop-up" code for CSUs, which is a repeating pattern of ...10000100001... , set TCD1 = 80h, IBCC = 0, and T1CCR1.0 = 1. The framer has three programmable pattern detectors. Typically two of the detectors are used for "loopup" and "loop-down" code detection. The user programs the codes to be detected in the receive up-code definition (RUPCD1 and RUPCD2) registers and the receive down-code definition (RDNCD1 and RDNCD2) registers, and the length of each pattern is selected through the IBCC register. There is a third detector (spare) that is defined and controlled through the RSCD1/RSCD2 and RSCC registers. When detecting a 16-bit pattern, both receive code-definition registers are used together to form a 16-bit register. For 8-bit patterns, both receive code-definition registers are filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code-definition register to be filled. The framer detects repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the receive code-definition register resets the integration period for that detector. The code detector has a nominal integration period of 36ms. Hence, after about 36ms of receiving a valid code, the proper status bit (LUP at SR3.5, LDN at SR3.6, and LSPARE at SR3.7) is set to a 1. Normally codes are sent for a period of five seconds. It is recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the code is continuously present.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 TC1 0 IBCC In-Band Code Control Register B6h 6 TC0 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 1 RDN1 0 0 RDN0 0
Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8/16
Bits 3 to 5/Receive Up-Code Length Definition Bits (RUP0 to RUP2) RUP2 0 0 0 0 1 1 1 1 RUP1 0 0 1 1 0 0 1 1 RUP0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8/16
Bits 6, 7/Transmit Code Length Definition Bits (TC0 to TC1) TC1 0 0 1 1 TC0 0 1 0 1 Length Selected (bits) 5 6/3 7 16/8/4/2/1
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TCD1 Transmit Code-Definition Register 1 B7h 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit 0/Transmit Code-Definition Bit 0 (C0). A don't care if a 5-, 6-, or 7-bit length is selected. Bit 1/Transmit Code-Definition Bit 1 (C1). A don't care if a 5-bit or 6-bit length is selected. Bit 2/Transmit Code-Definition Bit 2 (C2). A don't care if a 5-bit length is selected. Bits 3-6/Transmit Code-Definition Bits 3-6 (C3-C6) Bit 7/Transmit Code-Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TCD2 Transmit Code Definition Register 2 B8h 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Least significant byte of 16 bit codes.
Bits 0-7/Transmit Code-Definition Bits 0-7 (C0-C7). A don't care if a 5-, 6-, or 7-bit length is selected.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RUPCD1 Receive Up-Code Definition Register 1 B9h 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Note: Writing this register resets the detector's integration period.
Bit 0/Receive Up-Code Definition Bits 0 (C0). A don't care if a 1-bit to 7-bit length is selected. Bit 1/Receive Up-Code Definition Bit 1 (C1). A don't care if a 1-bit to 6-bit length is selected. Bit 2/Receive Up-Code Definition Bit 2 (C2). A don't care if a 1-bit to 5-bit length is selected. Bit 3/Receive Up-Code Definition Bit 3 (C3). A don't care if a 1-bit to 4-bit length is selected. Bit 4/Receive Up-Code Definition Bit 4 (C4). A don't care if a 1-bit to 3-bit length is selected. Bit 5/Receive Up-Code Definition Bit 5 (C5). A don't care if a 1-bit or 2-bit length is selected. Bit 6/Receive Up-Code Definition Bit 6 (C6). A don't care if a 1-bit length is selected. Bit 7/Receive Up-Code Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RUPCD2 Receive Up-Code Definition Register 2 BAh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bits 0-7/Receive Up-Code Definition Bits 0-7 (C0-C7). A don't care if a 1-bit to 7-bit length is selected.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RDNCD1 Receive Down-Code Definition Register 1 BBh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Note: Writing this register resets the detector's integration period.
Bit 0/Receive Down-Code Definition Bit 0 (C0). A don't care if a 1-bit to 7-bit length is selected. Bit 1/Receive Down-Code Definition Bit 1 (C1). A don't care if a 1-bit to 6-bit length is selected. Bit 2/Receive Down-Code Definition Bit 2 (C2). A don't care if a 1-bit to 5-bit length is selected. Bit 3/Receive Down-Code Definition Bit 3 (C3). A don't care if a 1-bit to 4-bit length is selected. Bit 4/Receive Down-Code Definition Bit 4 (C4). A don't care if a 1-bit to 3-bit length is selected. Bit 5/Receive Down-Code Definition Bit 5 (C5). A don't care if a 1-bit or 2-bit length is selected. Bit 6/Receive Down-Code Definition Bit 6 (C6). A don't care if a 1-bit length is selected. Bit 7/Receive Down-Code Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RDNCD2 Receive Down-Code Definition Register 2 BCh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bits 0-7/Receive Down-Code Definition Bits 0-7 (C0-C7). A don't care if a 1-bit to 7-bit length is selected.
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Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
RSCC In-Band Receive Spare Control Register BDh 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 RSC2 0 1 RSC1 0 0 RSC0 0
Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 0 0 0 0 1 1 1 1 RSC1 0 0 1 1 0 0 1 1 RSC0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8/16
Bits 3 to 7/Unused, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RSCD1 Receive Spare-Code Definition Register 1 BEh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Note: Writing this register resets the detector's integration period.
Bit 0/Receive Spare-Code Definition Bit 0 (C0). A don't care if a 1-bit to 7-bit length is selected. Bit 1/Receive Spare-Code Definition Bit 1 (C1). A don't care if a 1-bit to 6-bit length is selected. Bit 2/Receive Spare-Code Definition Bit 2 (C2). A don't care if a 1-bit to 5-bit length is selected. Bit 3/Receive Spare-Code Definition Bit 3 (C3). A don't care if a 1-bit to 4-bit length is selected. Bit 4/Receive Spare-Code Definition Bit 4 (C4). A don't care if a 1-bit to 3-bit length is selected. Bit 5/Receive Spare-Code Definition Bit 5 (C5). A don't care if a 1-bit or 2-bit length is selected. Bit 6/Receive Spare-Code Definition Bit 6 (C6). A don't care if a 1-bit length is selected. Bit 7/Receive Spare-Code Definition Bit 7 (C7). First bit of the repeating pattern. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 RSCD2 Receive Spare Code Definition Register 2 BFh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bits 0-7/Receive Spare-Code Definition Bits 0-7 (C0-C7). A don't care if a 1-bit to 7-bit length is selected.
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26.
BERT FUNCTION
The BERT block can generate and detect pseudorandom and repeating bit patterns. It is used to test and stress data communication links, and it is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words that flip every 1 to 256 words Daly pattern
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver reports three events: a change in receive synchronizer status, a bit error being detected, and if either the bit counter or the error counter overflows. Each of these events can be masked within the BERT function through the BERT control register 1 (BC1). If the software detects that the BERT has reported an event, then the software must read the BERT information register (BIR) to determine which event(s) has occurred. To activate the BERT block, the host must configure the BERT mux through the BIC register.
26.1 Status
SR9 contains the status information on the BERT function. The host can be alerted through this register when there is a BERT change-of-state. A major change-of-state is defined as either a change in the receive synchronization (i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the bit counter or the error counter. The host must read status register 9 (SR9) to determine the change-of-state.
26.2 Mapping
The BERT function can be assigned to the network direction or backplane direction through the direction control bit in the BIC register (BIC.1). See Figure 26-1 and Figure 26-2. The BERT also can be assigned on a per-channel basis. The BERT transmit control selector (BTCS) and BERT receive control selector (BRCS) bits of the per-channel pointer register (PCPR) are used to map the BERT function into time slots of the transmit and receive data streams. In T1 mode, the user can enable mapping into the F-bit position for the transmit and receive directions through the RFUS and TFUS bits in the BERT interface control (BIC) register.
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Figure 26-1. Simplified Diagram of BERT in Network Direction
FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING
TO RECEIVE SYSTEM BACKPLANE INTERFACE
BERT RECEIVER
BERT TRANSMITTER
TO TRANSMIT FRAMER
1 0
FROM TRANSMIT SYSTEM BACKPLANE INTERFACE
Figure 26-2. Simplified Diagram of BERT in Backplane Direction
FROM RECEIVE FRAMER
0 1
TO RECEIVE SYSTEM BACKPLANE INTERFACE
PER-CHANNEL AND F-BIT (T1 MODE) MAPPING BERT RECEIVER TO TRANSMIT FRAMER BERT TRANSMITTER FROM TRANSMIT SYSTEM BACKPLANE INTERFACE
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26.3 BERT Register Descriptions
Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 E0h 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0
Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization. Bit 1/Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into registers BBC1/BBC2/BBC3/BBC4 and BEC1/BEC2/BEC3 and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for subsequent loads. Bits 2 to 4/Pattern Select Bits (PS0 to PS2) PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Pattern Definition Pseudorandom 2E7 - 1 Pseudorandom 2E11 - 1 Pseudorandom 2E15 - 1 Pseudorandom pattern QRSS. A 220 - 1 pattern with 14 consecutive zero restrictions. Repetitive pattern Alternating word pattern Modified 55 octet (Daly) pattern. The Daly pattern is a repeating 55 octet pattern that is byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25 (November 1993). Pseudorandom 2E9 - 1
Bit 5/Receive Invert-Data Enable (RINV) 0 = do not invert the incoming data stream 1 = invert the incoming data stream Bit 6/Transmit Invert-Data Enable (TINV) 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream Bit 7/Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for subsequent loads.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 EIB2 0 BC2 BERT Control Register 2 E1h 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0
Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns fewer than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). Length (bits) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RPL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RPL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RPL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RPL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bit 4/Single Bit-Error Insert (SBE). A low-to-high transition creates a single-bit error. Must be cleared and set again for a subsequent bit error to be inserted. Bits 5 to 7/Error Insert Bits 0 to 2 (EIB0 to EIB2). Automatically inserts bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error-detection features. EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 Error Rate Inserted No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 SR9 Status Register 9 26h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0
Bit 0/BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive bit positions. Refer to BSYNC in the INFO2 register for a real-time version of this bit. This is a double interrupt bit (Section 6.2). Bit 1/BERT Receive Loss-of-Synchronization Condition (BRLOS). A latched bit that is set whenever the receive BERT begins searching for a pattern. Once synchronization is achieved, this bit remains set until read. This is a double interrupt bit (Section 6.2). Bit 2/BERT Receive All-Zeros Condition (BRA0). A latched bit that is set when 32 consecutive 0s are received. Allowed to be cleared once a 1 is received. This is a double interrupt bit (Section 6.2). Bit 3/BERT Receive All-Ones Condition (BRA1). A latched bit that is set when 32 consecutive 1s are received. Allowed to be cleared once a 0 is received. This is a double interrupt bit (Section 6.2). Bit 4/BERT Error-Counter Overflow (BECO) Event (BECO). A latched bit that is set when the 24-bit BERT error counter (BEC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 5/BERT Bit-Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter (BBC) overflows. Cleared when read and is not set again until another overflow occurs. Bit 6/BERT Bit-Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Cleared when read.
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 IMR9 Interrupt Mask Register 9 27h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0
Bit 0/BERT in Synchronization Condition (BSYNC) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 1/Receive Loss-of-Synchronization Condition (BRLOS) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 2/Receive All-Zeros Condition (BRA0) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 3/Receive All-Ones Condition (BRA1) 0 = interrupt masked 1 = interrupt enabled--interrupts on rising and falling edges Bit 4/BERT Error-Counter Overflow Event (BECO) 0 = interrupt masked 1 = interrupt enabled Bit 5/BERT Bit-Counter Overflow Event (BBCO) 0 = interrupt masked 1 = interrupt enabled Bit 6/Bit-Error Detected Event (BBED) 0 = interrupt masked 1 = interrupt enabled BERT Alternating Word-Count Rate. When the BERT is programmed in the alternating word mode, the words repeat for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this register. Register Name: Register Description: Register Address: Bit # Name Default 7 ACNT7 0 BAWC BERT Alternating Word-Count Rate DBh 6 ACNT6 0 5 ACNT5 0 4 ACNT4 0 3 ACNT3 0 2 ACNT2 0 1 ACNT1 0 0 ACNT0 0
Bits 0 to 7/Alternating Word-Count Rate Bits 0 to 7 (ACNT0 to ACNT7). ACNT0 is the LSB of the 8-bit alternating word-count rate counter.
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26.4 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the repeating 5-bit pattern ...01101... (where the rightmost bit is the one sent first and received first), then BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 with 5Ah. For a pseudorandom pattern, all four registers should be loaded with all 1s (i.e., FFh). For an alternating word pattern, one word should be placed into BRP1 and BRP2 and the other word should be placed into BRP3 and BRP4. For example, if the DDS stress pattern "7E" is to be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in BRP3, and 7Eh in BRP4 and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received.
Register Name: Register Description: Register Address: Bit # Name Default 7 RPAT7 0 BRP1 BERT Repetitive Pattern Set Register 1 DCh 6 RPAT6 0 5 RPAT5 0 4 RPAT4 0 3 RPAT3 0 2 RPAT2 0 1 RPAT1 0 0 RPAT0 0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 0 to 7 (RPAT0 to RPAT7). RPAT0 is the LSB of the 32-bit repetitive pattern set. Register Name: Register Description: Register Address: Bit # Name Default 7 RPAT15 0 BRP2 BERT Repetitive Pattern Set Register 2 DDh 6 RPAT14 0 5 RPAT13 0 4 RPAT12 0 3 RPAT11 0 2 RPAT10 0 1 RPAT9 0 0 RPAT8 0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 8 to 15 (RPAT8 to RPAT15) Register Name: Register Description: Register Address: Bit # Name Default 7 RPAT23 0 BRP3 BERT Repetitive Pattern Set Register 3 DEh 6 RPAT22 0 5 RPAT21 0 4 RPAT20 0 3 RPAT19 0 2 RPAT18 0 1 RPAT17 0 0 RPAT16 0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 16 to 23 (RPAT16 to RPAT23) Register Name: Register Description: Register Address: Bit # Name Default 7 RPAT31 0 BRP4 BERT Repetitive Pattern Set Register 4 DFh 6 RPAT30 0 5 RPAT29 0 4 RPAT28 0 3 RPAT27 0 2 RPAT26 0 1 RPAT25 0 0 RPAT24 0
Bits 0 to 7/BERT Repetitive Pattern Set Bits 24 to 31 (RPAT24 to RPAT31). RPAT31 is the LSB of the 32-bit repetitive pattern set. 206 of 262
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26.5 BERT Bit Counter
Once BERT has achieved synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BBCO status bit.
Register Name: Register Description: Register Address: Bit # Name Default 7 BBC7 0 BBC1 BERT Bit Count Register 1 E3h 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0
Bits 0 to 7/BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7). BBC0 is the LSB of the 32-bit counter. Register Name: Register Description: Register Address: Bit # Name Default 7 BBC15 0 BBC2 BERT Bit Count Register 2 E4h 6 BBC14 0 5 BBC13 0 4 BBC12 0 3 BBC11 0 2 BBC10 0 1 BBC9 0 0 BBC8 0
Bits 0 to 7/BERT Bit Counter Bits 8 to 15 (BBC8 to BBC15) Register Name: Register Description: Register Address: Bit # Name Default 7 BBC23 0 BBC3 BERT Bit Count Register 3 E5h 6 BBC22 0 5 BBC21 0 4 BBC20 0 3 BBC19 0 2 BBC18 0 1 BBC17 0 0 BBC16 0
Bits 0 to 7/BERT Bit Counter Bits 16 to 23 (BBC16 to BBC23) Register Name: Register Description: Register Address: Bit # Name Default 7 BBC31 0 BBC4 BERT Bit Count Register 4 E6h 6 BBC30 0 5 BBC29 0 4 BBC28 0 3 BBC27 0 2 BBC26 0 1 BBC25 0 0 BBC24 0
Bits 0 to 7/BERT Bit Counter Bits 24 to 31 (BBC24 to BBC31). BBC31 is the MSB of the 32-bit counter.
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26.6 BERT Error Counter
Once BERT has achieved synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BECO status bit.
Register Name: Register Description: Register Address: Bit # Name Default 7 EC7 0 BEC1 BERT Error-Count Register 1 E7h 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0
Bits 0 to 7/Error Counter Bits 0 to 7 (EC0 to EC7). EC0 is the LSB of the 24-bit counter. Register Name: Register Description: Register Address: Bit # Name Default 7 EC15 0 BEC2 BERT Error-Count Register 2 E8h 6 EC14 0 5 EC13 0 4 EC12 0 3 EC11 0 2 EC10 0 1 EC9 0 0 EC8 0
Bits 0 to 7/Error Counter Bits 8 to 15 (EC8 to EC15) Register Name: Register Description: Register Address: Bit # Name Default 7 EC23 0 BEC3 BERT Error-Count Register 3 E9h 6 EC22 0 5 EC21 0 4 EC20 0 3 EC19 0 2 EC18 0 1 EC17 0 0 EC16 0
Bits 0 to 7/Error Counter Bits 16 to 23 (EC16 to EC23). EC0 is the MSB of the 24-bit counter.
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Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0
BIC BERT Interface Control Register EAh 6 RFUS 0 5 -- 0 4 TBAT 0 3 TFUS 0 2 -- 0 1 BERTDIR 0 0 BERTEN 0
Bit 0/BERT Enable (BERTEN) 0 = BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR) 0 = network BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and RRING). The BERT pattern can be looped back to the receiver internally by using the framer loopback function. 1 = system BERT transmits toward the system backplane (RSER) and receives from the system backplane (TSER). Bits 2, 5, 7/Unused, must be set to 0 for proper operation Bit 3/Transmit Framed/Unframed Select (TFUS) 0 = BERT does not source data into the F-bit position (framed) 1 = BERT does source data into the F-bit position (unframed) Bit 4/Transmit Byte-Align Toggle (TBAT). A 0-to-1 transition forces the BERT to byte align its pattern with the transmit formatter. This bit must be transitioned in order to byte align the Daly pattern. Bit 6/Receive Framed/Unframed Select (RFUS) 0 = BERT is not sent data from the F-bit position (framed) 1 = BERT is sent data from the F-bit position (unframed)
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27.
PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)
An error-insertion function is available in the DS2156 and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 mode. Errors can be inserted over the entire frame or the user can select which channels are to be corrupted. Errors are created by inverting the last bit in the count sequence. For example, if the error rate 1 in 16 is selected, the 16th bit is inverted. F-bits are excluded from the count and are never corrupted. Error rate changes occur on frame boundaries. Error-insertion options include continuous and absolute number with both options supporting selectable insertion rates.
Table 27-A. Transmit Error-Insertion Setup Sequence
STEP 1 2A or 2B ACTION Enter desired error rate in the ERC register. Note: If ER3 through ER0 = 0, no errors are generated even if the constant error-insertion feature is enabled. For constant error insertion, set CE = 1 (ERC.4). For a defined number of errors: - Set CE = 0 (ERC.4) - Load NOE1 and NOE2 with the number of errors to be inserted - Toggle WNOE (ERC.7) from 0 to 1 to begin error insertion
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 WNOE 0 ERC Error-Rate Control Register EBh 6 -- 0 5 -- 0 4 CE 0 3 ER3 0 2 ER2 0 1 ER1 0 0 ER0 0
Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3) ER3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ER2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ER1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ER0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Error Rate No errors inserted 1 in 16 1 in 32 1 in 64 1 in 128 1 in 256 1 in 512 1 in 1024 1 in 2048 1 in 4096 1 in 8192 1 in 16,384 1 in 32,768 1 in 65,536 1 in 131,072 1 in 262,144
Bit 4/Constant Errors (CE). When this bit is set high (and the ER0 to ER3 bits are not set to 0000), the errorinsertion logic ignores the number-of-error registers (NOE1, NOE2) and generates errors constantly at the selected insertion rate. When CE is set to 0, the NOEx registers determine how many errors are to be inserted. Bits 5, 6/Unused, must be set to 0 for proper operation Bit 7/Write NOE Registers (WNOE). If the host wishes to update to the NOEx registers, this bit must be toggled from a 0 to a 1 after the host has already loaded the prescribed error count into the NOEx registers. The toggling of this bit causes the error count loaded into the NOEx registers to be loaded into the error-insertion circuitry on the next clock cycle. Subsequent updates require that the WNOE bit be set to 0 and then 1 once again.
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27.1 Number-of-Errors Registers
The number-of-error registers determine how many errors are generated. Up to 1023 errors can be generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update the number of errors to be created by first loading the prescribed value into the NOE registers and then toggling the WNOE bit in the error-rate control registers.
Table 27-B. Error Insertion Examples
VALUE 000h 001h 002h 3FFh WRITE Do not create any errors Create a single error Create two errors Create 1023 errors READ No errors left to be inserted One error left to be inserted Two errors left to be inserted 1023 errors left to be inserted
Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0
NOE1 Number-of-Errors 1 ECh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bits 0 to 7/Number-of-Errors Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 NOE2 Number-of-Errors 2 EDh 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 C9 0 0 C8 0
Bits 0, 1/Number-of-Errors Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter.
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27.1.1 Number-of-Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted.
Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 NOEL1 Number-of-Errors Left 1 EEh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bits 0 to 7/Number-of-Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter. Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 NOEL2 Number-of-Errors Left 2 EFh 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 C9 0 0 C8 0
Bits 0, 1/Number-of-Errors Left Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter.
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28.
INTERLEAVED PCM BUS OPERATION (IBO)
Note: The interleaved PCM bus operation is not available when UTOPIA backplane is enabled. In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS2156 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS2156 can be configured for channel or frame interleave. The interleaved PCM bus operation (IBO) supports three bus speeds. The 4.096MHz bus speed allows two PCM data streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to share a common bus. The 16.384MHz bus speed allows eight PCM data streams to share a common bus. See Figure 28-1 for an example of four transceivers sharing a common 8.192MHz PCM bus. The receive elastic stores of each transceiver must be enabled. Through the IBO register, the user can configure each transceiver for a specific bus position. For all IBO bus configurations, each transceiver is assigned an exclusive position in the high-speed PCM bus. The 8kHz frame sync can be generated from the system backplane or from the first device on the bus. All other devices on the bus must have their frame syncs configured as inputs. Relative to this common frame sync, the devices await their turn to drive or sample the bus according to the settings of the DA0, DA1, and DA2 bits of the IBOC register.
28.1 Channel Interleave
In channel interleave mode, data is output to the PCM data-out bus one channel at a time from each of the connected DS2156s until all channels of frame n from each DS2156 have been placed on the bus. This mode can be used even when the DS2156s are operating asynchronous to each other. The elastic stores manage slip conditions (Figure 34-22).
28.2 Frame Interleave
In frame interleave mode, data is output to the PCM data-out bus one frame at a time from each of the DS2156s. This mode is used only when all connected DS2156s are operating in a synchronous fashion (all inbound T1 or E1 lines are synchronous) and are synchronous with the system clock (system clock derived from T1 or E1 line). Slip conditions are not allowed in this mode (Figure 34-23).
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 IBOC Interleave Bus Operation Control Register C5h 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0
Bits 0 to 2/Device Assignment Bits (DA0 to DA2) DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position on Bus 1st 2nd 3rd 4th 5th 6th 7th 8th
Bit 3/Interleave Bus Operation Enable (IBOEN) 0 = IBO disabled 1 = IBO enabled Bit 4/Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = channel interleave 1 = frame interleave Bits 5, 6/IBO Bus Size Bit 1 (IBS0 to IBS1). Indicates how many devices are on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size Two devices on bus Four devices on bus Eight devices on bus Reserved for future use
Bit 7/Unused, must be set to 0 for proper operation
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Figure 28-1. IBO Example
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG
DS2156 #1 RSER
TSER
DS2156 #3 RSER
8.192MHz SYSTEM CLOCK IN SYSTEM 8kHz FRAME SYNC IN PCM SIGNALING OUT PCM SIGNALING IN PCM DATA IN PCM DATA OUT
TSER
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG
RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG
DS2156 #2 RSER
TSER
DS2156 #4 RSER
TSER
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29.
EXTENDED SYSTEM INFORMATION BUS (ESIB)
The extended system information bus (ESIB) allows up to eight DS2156s to share an 8-bit CPU bus for reporting alarms and interrupt status as a group. With a single bus read, the host can be updated with alarm or interrupt status from all members of the group. There are two control registers (ESIBCR1 and ESIBCR2) and four information registers (ESIB1, ESIB2, ESIB3, and ESIB4). For example, eight DS2156s can be grouped into an ESIB group. A single read of the ESIB1 register of any member of the group yields the interrupt status of all eight DS2156s. Therefore, the host can determine which device or devices are causing an interrupt without polling all eight devices. Through ESIB2, the host can gather synchronization status on all members of the group. ESIB3 and ESIB4 can be programmed to report various alarms on a device-by-device basis. There are three device pins involved in forming an ESIB group: ESIBS0, ESIBS1, and ESIBRD. A 10k pullup resistor must be provided on ESIBS0, ESIBS1, and ESIBRD.
Figure 29-1. ESIB Group of Four DS2156s
VDD
10k (3)
DS2156 # 1
CPU I/F ESIB0 ESIB1 ESIBRD
DS2156 # 2
CPU I/F ESIB0 ESIB1 ESIBRD
DS2156 # 3
CPU I/F ESIB0 ESIB1 ESIBRD
DS2156 # 4
CPU I/F ESIB0 ESIB1 ESIBRD
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 ESIBCR1 Extended System Information Bus Control Register 1 B0h 6 -- 0 5 -- 0 4 -- 0 3 ESIBSEL2 0 2 ESIBSEL1 0 1 ESIBSEL0 0 0 ESIEN 0
Bit 0/Extended System Information Bus Enable (ESIEN) 0 = disabled 1 = enabled Bits 1 to 3/Output Data Bus Line Select (ESIBSEL0 to ESIBSEL2). These bits tell the DS2156 what data bus bit to output the ESIB data on when one of the ESIB information registers is accessed. Each member of the ESIB group must have a unique bit selected. ESIBSEL2 0 0 0 0 1 1 1 1 ESIBSEL1 0 0 1 1 0 0 1 1 ESIBSEL0 0 1 0 1 0 1 0 1 Bus Bit Driven AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Bits 4 to 7/Unused, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 ESIBCR2 Extended System Information Bus Control Register 2 B1h 5 ESI4SEL1 0 4 ESI4SEL0 0 3 -- 0 2 ESI3SEL2 0 1 ESI3SEL1 0 0 ESI3SEL0 0
6 ESI4SEL2 0
Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be output when the DS2156 decodes an ESI3 address during a bus read operation. ESI3SEL2 0 0 0 0 1 1 1 1 ESI3SEL1 0 0 1 1 0 0 1 1 ESI3SEL0 0 1 0 1 0 1 0 1 Status Output (T1 Mode) RBL RYEL LUP LDN SIGCHG ESSLIP -- -- Status Output (E1 Mode) RUA1 RRA RDMA V52LNK SIGCHG ESSLIP -- --
Bit 3/Unused, must be set to 0 for proper operation Bits 4 to 6/Address ESI4 Data-Output Select (ESI4SEL0 to ESI4SEL2). These bits select what status is to be output when the DS2156 decodes an ESI4 address during a bus read operation. ESI4SEL2 0 0 0 0 1 1 1 1 ESI4SEL1 0 0 1 1 0 0 1 1 ESI4SEL0 0 1 0 1 0 1 0 1 Status Output (T1 Mode) RBL RYEL LUP LDN SIGCHG ESSLIP -- -- Status Output (E1 Mode) RUA1 RRA RDMA V52LNK SIGCHG ESSLIP -- --
Bit 7/Unused, must be set to 0 for proper operation
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DS2156 Register Name: Register Description: Register Address: Bit # Name Default 7 DISn 0 ESIB1 Extended System Information Bus Register 1 B2h 6 DISn 0 5 DISn 0 4 DISn 0 3 DISn 0 2 DISn 0 1 DISn 0 0 DISn 0
Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their interrupt status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Register Name: Register Description: Register Address: Bit # Name Default 7 DRLOSn 0
ESIB2 Extended System Information Bus Register 2 B3h 6 DRLOSn 0 5 DRLOSn 0 4 DRLOSn 0 3 DRLOSn 0 2 DRLOSn 0 1 DRLOSn 0 0 DRLOSn 0
Bits 0 to 7/Device Receive Loss-of-Sync (DRLOSn). Causes all devices participating in the ESIB group to output their frame synchronization status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Register Name: Register Description: Register Address: Bit # Name Default 7 UST1n 0
ESIB3 Extended System Information Bus Register 3 B4h 6 UST1n 0 5 UST1n 0 4 UST1n 0 3 UST1n 0 2 UST1n 0 1 UST1n 0 0 UST1n 0
Bits 0 to 7/User-Selected Status 1 (UST1n). Causes all devices participating in the ESIB group to output status or alarms as selected by the ESI3SEL0 to ESI3SEL2 bits in the ESIBCR2 configuration register on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register
Register Name: Register Description: Register Address: Bit # Name Default 7 UST2n 0
ESIB4 Extended System Information Bus Register 4 B5h 6 UST2n 0 5 UST2n 0 4 UST2n 0 3 UST2n 0 2 UST2n 0 1 UST2n 0 0 UST2n 0
Bits 0 to 7/User-Selected Status 2 (UST2n). Causes all devices participating in the ESIB group to output status or alarms as selected by the ESI4SEL0 to ESI4SEL2 bits in the ESIBCR2 configuration register on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register
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30.
PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER
The DS2156 contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common applications include generation of port and backplane system clocks. The CCR2 register is used to enable (CCR2.0) and select (CCR2.1 and CCR2.2) the clock frequency of the BPCLK pin.
Register Name: Register Description: Register Address: Bit # Name Default 7 TRPA4 0 CCR2 Common Control Register 2 71h 6 TRPA3 0 5 TRPA2 0 4 TRPA1 0 3 TRPA0 0 2 BPCS1 0 1 BPCS0 0 0 BPEN 0
Bit 0/Backplane Clock Enable (BPEN) 0 = disable BPCLK pin (pin held at logic 0) 1 = enable BPCLK pin Bits 1, 2/Backplane Clock Selects (BPCS0, BPCS1) BPCS1 0 0 1 1 BPCS0 0 1 0 1 BPCLK Frequency (MHz) 16.384 8.192 4.096 2.048
Bits 3 to 7/UTOPIA Port Address (TRPA0 to TRPA4). See Register Definitions in Section 24.7.
31.
FRACTIONAL T1/E1 SUPPORT
31.1 TDM Backplane Mode
The DS2156 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDNPRI applications. The receive and transmit paths have independent enables. Channel formats supported include 56kbps and 64kbps. This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins. Setting CCR3.0 = 1 causes the RCHCLK pin to output a gapped clock as defined by the receive fractional T1/E1 function of the PCPR register. Setting CCR3.2 = 1 causes the TCHCLK pin to output a gapped clock as defined by the transmit fractional T1/E1 function of the PCPR register. CCR3.1 and CCR3.3 can be used to select between 64kbps and 56kbps operation. See Section 5 for details about programming the per-channel function. In T1 mode no clock is generated at the F-bit position. When 56kbps mode is selected, the LSB clock in the channel is omitted. Only the seven most significant bits of the channel have clocks.
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31.2 UTOPIA Backplane Mode
ATM traffic can be assigned on a fractional basis. See Section 24 for UTOPIA operation.
Register Name: Register Description: Register Address: Bit # Name Default 7 TMSS 0 CCR3 Common Control Register 3 72h 5 CTTUI 0 4 CRRUI 0 3 TDATFMT 0 2 TGPCKEN 0 1 RDATFMT 0 0 RGPCKEN 0
6 INTDIS 0
Bit 0/Receive Gapped-Clock Enable (RGPCKEN) 0 = RCHCLK functions normally 1 = enable gapped bit-clock output on RCHCLK Bit 1/Receive Channel-Data Format (RDATFMT) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) Bit 2/Transmit Gapped-Clock Enable (TGPCKEN) 0 = TCHCLK functions normally 1 = enable gapped bit-clock output on TCHCLK Bit 3/Transmit Channel-Data Format (TDATFMT) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) Bit 4/Connect RCLK to Receive UTOPIA Interface (CRRUI). This bit selects either a constant clock (RCLK) or a gapped clock from the framer (programmed by the user) as its data clock. 0 = gated clock is connected to receive UTOPIA interface 1 = RCLK is connected to receive UTOPIA interface Bit 5/Connect TCLK to Transmit UTOPIA Interface (CTTUI). This bit selects either a constant clock (TCLK) or a gapped clock from the framer (programmed by the user) as its data clock. 0 = gated clock is connected to transmit UTOPIA interface 1 = TCLK is connected to transmit UTOPIA interface Bit 6/Interrupt Disable (INTDIS). This bit is convenient for disabling interrupts without altering the various interrupt mask register settings. 0 = interrupts are enabled according to the various mask register settings 1 = interrupts are disabled regardless of the mask register settings Bit 7/Transmit Multiframe Sync Source (TMSS). Should be set = 0 only when transmit hardware signaling is enabled. 0 = elastic store is source of multiframe sync 1 = framer or TSYNC pin is source of multiframe sync
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32.
USER-PROGRAMMABLE OUTPUT PINS
The DS2156 provides four user-programmable output pins. The pins are automatically cleared to 0 at power-up or as a result of a hardware- or software-issued reset.
Register Name: Register Description: Register Address: Bit # Name Default 7 RLT3 0 CCR4 Common Control Register 4 73h 6 RLT2 0 5 RLT1 0 4 RLT0 0 3 UOP3 0 2 UOP2 0 1 UOP1 0 0 UOP0 0
Bit 0/User-Defined Output 0 (UOP0) 0 = logic 0 level at pin 1 = logic 1 level at pin Bit 1/User-Defined Output 1 (UOP1) 0 = logic 0 level at pin 1 = logic 1 level at pin Bit 2/User-Defined Output 2 (UOP2) 0 = logic 0 level at pin 1 = logic 1 level at pin Bit 3/User-Defined Output 3 (UOP3) 0 = logic 0 level at pin 1 = logic 1 level at pin Bits 4 to 7/Receive Level Threshold Bits (RLT0 to RLT3) RLT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RLT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RLT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RLT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Receive Level (dB) Greater than -2.5 -2.5 -5.0 -7.5 -10.0 -12.5 -15.0 -17.5 -20.0 -22.5 -25.0 -27.5 -30.0 -32.5 -35.0 Less than -37.5
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33.
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
33.1 Description
The DS2156 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z, CLAMP, and IDCODE (Figure 33-1.). The DS2156 contains the following features as required by IEEE 1149.1 standard test access port (TAP) and boundary scan architecture. Test Access Port TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register
The DS2156 is pin-compatible with the DS2152, DS21x52 (T1) and DS2154, DS21x54 (E1) SCT families. The JTAG feature uses pins that had no function in the DS2152 and DS2154. Details about boundary scan architecture and the TAP are in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The TAP contains the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in Section 3 for details.
Figure 33-1. JTAG Functional Block Diagram
BOUNDARY SCAN REGISTER
IDENTIFICATION REGISTER
BYPASS REGISTER MUX INSTRUCTION REGISTER SELECT TEST ACCESS PORT CONTROLLER +V 10k 10k +V +V OUTPUT ENABLE
10k
JTDI
JTMS
JTCLK
JTRST
JTDO
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 33-2). Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test registers remain idle. Select-DR-Scan All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. Capture-DR Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is LOW or it goes to the Exit1-DR state if JTMS is HIGH. Shift-DR The test data register selected by the current instruction is connected between JTDI and JTDO and shifts data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. Exit1-DR While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-DR state. Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH puts the controller in the Exit2-DR state. Exit2-DR A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state. Update-DR A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output because of changes in the shift register.
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Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the Shift-IR state. Shift-IR In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel register and all test registers remain at their previous states. A rising edge on JTCLK with JTMS HIGH moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW keeps the controller in the Shift-IR state while moving data one stage through the instruction shift register. Exit1-IR A rising edge on JTCLK with JTMS LOW puts the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. Exit2-IR A rising edge on JTCLK with JTMS LOW puts the controller in the Update-IR state. The controller loops back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state. Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW puts the controller in the Run-Test-Idle state. With JTMS HIGH, the controller enters the Select-DR-Scan state.
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Figure 33-2. TAP Controller State Diagram
1 Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1
0
33.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH moves the controller to the Update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS2156 and its respective operational binary codes are shown in Table 16-A.
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Table 33-A. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001
SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register through JTDI using the Shift-DR state. BYPASS When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device's normal operation. EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur: Once enabled through the Update-IR state, the parallel outputs of all digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR samples all digital inputs into the boundary scan register. CLAMP All digital outputs of the device output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction. HIGHZ All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between JTDI and JTDO. IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code is loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version (Table 33-B). Table 33-C lists the device ID codes for the SCT devices.
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Table 33-B. ID Code Structure
MSB Version Contact Factory 4 bits Device ID 16 bits JEDEC 00010100001 LSB 1 1
Table 33-C. Device ID Codes
PART DS2156 DS2155 DS21354 DS21564 DS21352 DS21562 16-BIT ID 0019h 0010h 0005h 0003h 0004h 0002h
33.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register. An optional test register, the identification register, has been included with the DS2156 design. It is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
33.4 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells. It is n bits in length. See Table 33-D for cell bit locations and definitions.
33.5 Bypass Register
This is a single one-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that provides a short path between JTDI and JTDO.
33.6 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See Table 33-B and Table 33-C for more information on bit usage.
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Table 33-D. Boundary Scan Control Bits
( ) = Alternate function when in UTOPIA backplane mode.
BIT 3 -- 2 1 -- -- 0 -- 98 97 96 95 94 93 92 91 90 89 -- -- -- -- -- -- 88 87 86 85 -- -- -- -- -- 84 83 82 81 80 79 78 77
PIN 1 2 -- 3 4 5 6 7 -- 8 -- 9 10 11 -- 12 13 14 15 16 17 18 19, 20, 24 21 22 -- 23 25 26 27, 28 29 30 31 32 -- 33 -- 34 35 -- 36 --
NAME RCHBLK (UR_SOC) JTMS BPCLK.cntl BPCLK (UR_ENB) JTCLK JTRST RCL JTDI UOP0.cntl UOP0 (UT_SOC) UOP1.cntl UOP1 (UT_ENB) JTDO BTS LIUC.cntl LIUC (UT_CLAV) 8XCLK TSTRST UOP2 RTIP RRING RVDD RVSS MCLK XTALD UOP3.cntl UOP3 (UT_ADDR0) INT TUSEL N.C. TTIP TVSS TVDD TRING TCHBLK.cntl TCHBLK (UT_ADDR1) TLCLK.cntl TLCLK (UT_ADDR2) TLINK (UT_ADDR3) ESIBS0.cntl ESIBS0 TSYNC.cntl
TYPE O I -- I/O I I O I -- I/O -- I/O O I -- I/O O I O I I -- -- I O -- I/O O I -- O -- -- O -- I/O -- I/O I -- I/O --
CONTROL BIT FUNCTION -- -- 0 = BPCLK is an input (UR_ENB) 1 = BPCLK is an output -- -- -- -- -- 0 = UOP0 is an input UT_SOC 1 = UOP0 is an output -- 0 = UOP1 is an input UT_ENB 1 = UOP1 is an output -- -- -- 0 = LIUC is an input 1 = LIUC is an output (UT_CLAV) -- -- -- -- -- -- -- -- -- -- 0 = UOP3 is an input (UT_ADDR0) 1 = UOP3 is an output -- -- -- -- -- -- -- -- 0 = TCHBLK is an input (UT_ADDR1) 1 = TCHBLK is an output -- 0 = TLCLK is an input (UT_ADDR2) 1 = TLCLK is an output -- -- 0 = ESIBS0 is an input 1 = ESIBS0 is an output -- 0 = TSYNC is an input
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BIT 76 75 74 73 72 71 70 69 68 67 -- -- 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 -- -- 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 PIN 37 38 39 40 -- 41 -- 42 -- 43 44 45 46 47 48 49 50 51 52 -- 53 -- 54 55 -- 56 57 58 59 60, 80, 84 61, 81, 83 62 63 64 65 66 67 68 69 70 71 72 73 74 75 -- NAME TSYNC TPOSI (UT_ADDR4) TNEGI (UT_DATA0) TCLKI (UT_DATA1) TCLKO.cntl TCLKO (UT_DATA2) TNEGO.cntl TNEGO (UT_DATA3) TPOSO.cntl TPOSO (UT_DATA4) DVDD DVSS TCLK TSER (UT_DATA5) TSIG (UT_DATA6) TESO (UT_UTDO) TDATA TSYSCLK (UT_DATA7) TSSYNC (UT_CLK) TCHCLK.cntl TCHCLK (UR_CLK) ESIBS1.cntl ESIBS1 MUX BUS.cntl D0/AD0 D1/AD1 D2/AD2 D3/AD3 DVSS DVDD D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE(AS)/A7 RD (DS) CS ESIBRD.cntl TYPE I/O I I I -- I/O -- I/O -- I/O -- -- I I I O I I I -- I/O -- I/O I -- I/O I/O I/O I/O -- -- I/O I/O I/O I/O I I I I I I I I I I -- 0 = TPOSO is an input (UT_DATA4) 1 = TPOSO is an output -- -- -- -- -- -- -- -- -- -- 0 = TCHCLK is an input (UR_CLK) 1 = TCHCLK is an output -- 0 = ESIBS1 is an input 1 = ESIBS1 is an output -- -- 0 = D0-D7/AD0-AD7 are inputs 1 = D0-D7/AD0-AD7 are inputs -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 = ESIBRD is an input 1 = ESIBRD is an output 0 = TNEGO is an input (UT_DATA3) 1 = TNEGO is an output (UT_DATA4) CONTROL BIT FUNCTION 1 = TSYNC is an output -- -- -- -- 0 = TCLKO is an input (UT_DATA2) 1 = TCLKO is an output
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BIT 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 PIN 76 77 78 79 82 85 -- 86 -- 87 -- 88 89 90 91 -- 92 -- 93 -- 94 95 -- 96 -- 97 -- 98 99 -- 100 NAME ESIBRD WR (R/W) RLINK (UR_DATA0) RLCLK (UR_DATA1) RCLK RDATA RPOSI.cntl RPOSI (UR_DATA2) RNEGI.cntl RNEGI (UR_DATA3) RCLKI.cntl RCLKI (UR_DATA4) RCLKO (UR_DATA5) RNEGO (UR_DATA6) RPOSO (UR_DATA7) RCHCLK.cntl RCHCLK (UR_ADDR0) RSIGF.cntl RSIGF (UR_ADDR1) RSIG.cntl RSIG (UR_ADDR2) RSER (UR_CLAV) RMSYNC.cntl RMSYNC (UR_ADDR3) RFSYNC.cntl RFSYNC (UR_ADDR4) RSYNC.cntl RSYNC RLOS/LOTC RSYSCLK.cntl RSYSCLK (UT_2CLAV) TYPE I/O I O O O O -- I/O -- I/O -- I/O O O O I/O I/O -- I/O -- I/O O -- I/O -- I/O -- I/O O -- I/O CONTROL BIT FUNCTION -- -- -- -- -- -- 0 = RPOSI is an input 1 = RPOSI is an output (UR_DATA2) -- 0 = RNEGI is an input 1 = RNEGI is an output (UR_DATA3) -- 0 = RCLKI is an input 1 = RCLKI is an output (UR_DATA4) -- -- -- -- 0 = RCHCLK is an input (UR_ADDR0) 1 = RCHCLK is an output -- 0 = RSIGF is an input (UR_ADDR1) 1 = RSIGF is an output -- 0 = RSIG is an input (UR_ADDR2) 1 = RSIG is an output -- -- 0 = RMSYNC is an input (UR_ADDR3) -- 0 = RFSYNC is an input (UR_ADDR4) 1 = RFSYNC is an output -- 0 = RSYNC is an input 1 = RSYNC is an output -- -- 0 = RSYSCLK is an input 1 = RSYSCLK in an output (UT_2CLAV) --
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34.
FUNCTIONAL TIMING DIAGRAMS
34.1 T1 Mode Figure 34-1. Receive-Side D4 Timing
FRAME# RFSYNC RSYNC 1 RSYNC 2 RSYNC
3
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
RLCLK RLINK
4
Note 1: RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0). Note 2: RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1). Note 3: RSYNC in the multiframe mode (IOCR1.5 = 1). Note 4: RLINK data (Fs bits) is updated one bit prior to even frames and held for two frames.
Figure 34-2. Receive-Side ESF Timing
FRAME# RSYNC
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5
RFSYNC RSYNC RSYNC RLCLK
2 3
4 5
RLINK
TLCLK 6 TLINK 7
Note 1: RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0). Note 2: RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1). Note 3: RSYNC in multiframe mode (IOCR1.4 = 1). Note 4: ZBTSI mode disabled (T1RCR2.2 = 0). Note 5: RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames. Note 6: ZBTSI mode is enabled (T1RCR2.2 = 1). Note 7: RLINK data (Z bits) is updated one bit time before odd frames and held for four frames.
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Figure 34-3. Receive-Side Boundary Timing (with elastic store disabled)
RCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB
CHANNEL 1
RSER RSYNC RFSYNC RSIG RCHCLK RCHBLK1 RLCLK RLINK 2
F
MSB
CHANNEL 23 A B C/A D/B
CHANNEL 24 A B C/A D/B
CHANNEL 1 A
Note 1: RCHBLK is programmed to block channel 24. Note 2: Shown is RLINK/RLCLK in the ESF framing mode.
Figure 34-4. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB
CHANNEL 1
RSER RSYNC1 RMSYNC RSYNC2 RSIG RCHCLK RCHBLK
3
F
MSB
CHANNEL 23 A B C/A D/B
CHANNEL 24 A B C/A D/B
CHANNEL 1 A
Note 1: RSYNC is in the output mode (IOCR1.4 = 0). Note 2: RSYNC is in the input mode (IOCR1.4 = 1). Note 3: RCHBLK is programmed to block channel 24.
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Figure 34-5. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
RSYSCLK RSER RSYNC
1 CHANNEL 31
LSB MSB
CHANNEL 32
LSB
CHANNEL 1
2
RMSYNC
RSYNC
3 CHANNEL 31 B C/A D/B CHANNEL 32 B C/A D/B CHANNEL 1
RSIG RCHCLK RCHBLK
4
A
A
Note 1: RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1. Note 2: RSYNC is in the output mode (IOCR1.4 = 0). Note 3: RSYNC is in the input mode (IOCR1.4 = 1). Note 4: RCHBLK is forced to 1 in the same channels as RSER (see Note 1). Note 5: The F-bit position is passed through the receive-side elastic store.
Figure 34-6. Transmit-Side D4 Timing
FRAME# TSYNC
1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
TSSYNC TSYNC TSYNC
2 3
TLCLK TLINK
4
Note 1: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0). Note 2: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1). Note 3: TSYNC in the multiframe mode (IOCR1.2 = 1). Note 4: TLINK data (Fs bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled through T1TCR1.2.
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Figure 34-7. Transmit-Side ESF Timing
FRAME# TSYNC1 TSSYNC TSYNC
2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5
TSYNC
TLCLK
TLINK TLCLK 5 TLINK
6
Note 1: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0). Note 2: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1). Note 3: TSYNC in multiframe mode (IOCR1.2 = 1). Note 4: TLINK data (FDL bits) sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled through TCR1.2. Note 5: ZBTSI mode is enabled (T1TCR2.1 = 1). Note 6: TLINK data (Z bits) sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled through T1TCR1.2.
Figure 34-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB LSB MSB
TSER TSYNC1 TSYNC2
LSB
F
MSB
CHANNEL 1
CHANNEL 2
C/A D/B A B C/A D/B
TSIG TCHCLK TCHBLK 3 TLCLK TLINK
4
D/B
A
B
DON'T CARE
Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TCHBLK is programmed to block channel 2. Note 4: Shown is TLINK/TLCLK in the ESF framing mode.
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Figure 34-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
TSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB F MSB
CHANNEL 1
TSER TSSYNC
CHANNEL 23
CHANNEL 24
C/A D/B A B C/A D/B
CHANNEL 1
A
TSIG TCHCLK TCHBLK 1
A
B
Note 1: TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG is ignored during channel 24).
Figure 34-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
TSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB
CHANNEL 1
TSER
1
F
4
TSSYNC
CHANNEL 31 CHANNEL 32
C/A D/B A B C/A D/B
CHANNEL 1
A
TSIG TCHCLK TCHBLK 2,3
A
B
Note 1: TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. Note 2: TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored). Note 3: TCHBLK is forced to 1 in the same channels as TSER is ignored (see Note 1). Note 4: The F-bit position for the T1 frame is sampled and passed through the transmit-side elastic store into the MSB bit position of channel 1. (Normally, the transmit-side formatter overwrites the F-bit position unless the formatter is programmed to pass through the F-bit position.)
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34.2 E1 Mode Figure 34-11. Receive-Side Timing
FRAME# RFSYNC RSYNC
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
RSYNC 2 RLCLK RLINK
3 4
Note 1: RSYNC in frame mode (IOCR1.5 = 0). Note 2: RSYNC in multiframe mode (IOCR1.5 = 1). Note 3: RLCLK is programmed to output just the Sa bits. Note 4: RLINK always outputs all five Sa bits as well as the rest of the receive data stream. Note 5: This diagram assumes the CAS MF begins in the RAF frame.
Figure 34-12. Receive-Side Boundary Timing (with Elastic Store Disabled)
RCLK
CHANNEL 32 CHANNEL 1
LSB
CHANNEL 2
RSER RSYNC RFSYNC
CHANNEL 32
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 1 C D
Note 4
RSIG RCHCLK RCHBLK
1
A
B
CHANNEL 2 A B
RLCLK RLINK
2 Sa4 Sa5 Sa6 Sa7 Sa8
Note 1: RCHBLK is programmed to block channel 1. Note 2: RLCLK is programmed to mark the Sa4 bit in RLINK. Note 3: Shown is a RNAF frame boundary. Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.
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Figure 34-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled)
RSYSCLK
CHANNEL 23/31 CHANNEL 24/32
LSB
CHANNEL 1/2
RSER
1
LSB MSB
F
MSB
RSYNC2 RMSYNC RSYNC
3
RCHCLK RCHBLK
4
Note 1: Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to on 1). Note 2: RSYNC in the output mode (IOCR1.4 = 0). Note 3: RSYNC in the input mode (IOCR1.4 = 1). Note 4: RCHBLK is programmed to block channel 24.
Figure 34-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic Store Enabled)
RSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB MSB
CHANNEL 1
RSER RSYNC1 RMSYNC
RSYNC
2
RSIG RCHCLK RCHBLK
3
A
CHANNEL 31 C B D
A
CHANNEL 32 C B D
CHANNEL 1
Note 4
Note 1: RSYNC is in the output mode (IOCR1.4 = 0). Note 2: RSYNC is in the input mode (IOCR1.4 = 1). Note 3: RCHBLK is programmed to block channel 1. Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.
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Figure 34-15. Receive IBO Channel Interleave Mode Timing
FRAMER #1, CHANNEL #1 RSYNC RSER
1 F2 C32 F2 C32
F3 32 F3 C32
F5 C32 F5 C32 F6 C32 F6 C32
F1 C1 F1 C1
F1 C1 F1 C1
F1 C1 F1 C1 F2 C1 F2 C1
F2 C1 F2 C1
F3 C1 F3 C1
F5 C1 F5 C1 F6 C1 F6 C1
F1 C2 F1 C2
F1 C2 F1 C2
F1 C2 F1 C2 F2 C2 F2 C2
F2 C2 F2 C2
F3 C2 F3 C2
F5 C2 F5 C2 F6 C2 F6 C2
1 RSIG
RSER2 RSIG2 RSER3 RSIG3
F4 32 F4 C32
F7 C32 F7 C32 F8 C32 F8 C32
F2 C1 F2 C1
F3 C1 F3 C1 F4 C1 F4 C1
F4 C1 F4 C1
F7 C1 F7 C1 F8 C1 F8 C1
F2 C2 F2 C2
F3 C2 F3 C2 F4 C2 F4 C2
F4 C2 F4 C2
F7 C2 F7 C2 F8 C2 F8 C2
BIT LEVEL DETAIL (4.096MHz bus configurtation) RSYSCLK RSYNC
4 FRAMER2, CHANNEL 32 FRAMER 1, CHANNEL 1
LSB MSB
FRAMER2, CHANNEL 1
LSB
RSER RSIG
A B C
LSB MSB
FRAMER2, CHANNEL 32
D
FRAMER 1, CHANNEL 1
A B C D
FRAMER2, CHANNEL 1
A B C D
Note 1: 4.096MHz bus configuration. Note 2: 8.192MHz bus configuration. Note 3: 16.384MHz bus configuration. Note 4: RSYNC is in the input mode (IOCR1.4 = 0).
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Figure 34-16. Receive IBO Frame Interleave Mode Timing
FRAMER #1, CHANNELS 1 through 32 RSYNC RSER
1 F2 F2
F3 F3
F5 F6 F7
F1 F1
F4 F4
F8 F1
F2 F2
F2 F2 F3 F3
F5 F6 F7
F1 F1
F4 F4
F8 F1
F2 F2
F2 F2 F3 F3
F4 F5 F6 F7
1 RSIG
RSER2 RSIG2 RSER3 RSIG3
F1 F1
F2 F3
F1 F1
F2 F3
F4 F4
F8
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
BIT LEVEL DETAIL (4.096MHz bus configurtation) RSYSCLK RSYNC
4 FRAMER2, CHANNEL 32 FRAMER 1, CHANNEL 1
LSB MSB
FRAMER1, CHANNEL 2
LSB
RSER RSIG
A B C
LSB MSB
FRAMER2, CHANNEL 32
D
FRAMER 1, CHANNEL 1
A B C D
FRAMER1, CHANNEL 2
A B C D
Note 1: 4.096MHz bus configuration. Note 2: 8.192MHz bus configuration. Note 3: 16.384MHz bus configuration. Note 4: RSYNC is in the input mode (IOCR1.4 = 0).
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Figure 34-17. G.802 Timing, E1 Mode Only
TS # RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK
31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2
RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER RCHCLK / TCHCLK RCHBLK / TCHBLK
LSB MSB
CHANNEL 26
Note 1: RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of time slot 26.
Figure 34-18. Transmit-Side Timing
FRAME# TSYNC
1 14 15 16 1 2 3 4 56 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10
TSSYNC TSYNC TLCLK TLINK
2 3 3
Note 1: TSYNC in frame mode (IOCR1.2 = 0). Note 2: TSYNC in multiframe mode (IOCR1.2 = 1). Note 3: TLINK is programmed to source just the Sa4 bit. Note 4: This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame. Note 5: TLINK and TLCLK are not synchronous with TSSYNC.
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Figure 34-19. Transmit-Side Boundary Timing (Elastic Store Disabled)
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB
TSER TSYNC1 TSYNC2
LSB
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 1
CHANNEL 2
A B C D
TSIG TCHCLK TCHBLK 3 TLCLK TLINK
4 4
D
DON'T CARE
DON'T CARE
Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TCHBLK is programmed to block channel 2. Note 4: TLINK is programmed to source the Sa4 bit. Note 5: The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS MF alignment nibble (0000). Note 6: Shown is a TNAF frame boundary.
Figure 34-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled)
TSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB F MSB
CHANNEL 1
TSER
1
TSSYNC TCHCLK TCHBLK
2
Note 1: The F-bit position in the TSER data is ignored. Note 2: TCHBLK is programmed to block channel 24.
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Figure 34-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled)
TSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB
CHANNEL 1
TSER
1
F
4
TSSYNC
CHANNEL 31 CHANNEL 32
C D A B C D
CHANNEL 1
A
TSIG TCHCLK TCHBLK 2,3
A
B
Note 1: TCHBLK is programmed to block channel 31.
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Figure 34-22. Transmit IBO Channel Interleave Mode Timing
FRAMER #1, CHANNEL #1 TSSYNC TSER
1 F2 C32 F2 C32
F3 32 F3 C32
F5 C32 F5 C32 F6 C32 F6 C32
F1 C1 F1 C1
F1 C1 F1 C1
F1 C1 F1 C1 F2 C1 F2 C1
F2 C1 F2 C1
F3 C1 F3 C1
F5 C1 F5 C1 F6 C1 F6 C1
F1 C2 F1 C2
F1 C2 F1 C2
F1 C2 F1 C2 F2 C2 F2 C2
F2 C2 F2 C2
F3 C2 F3 C2
F5 C2 F5 C2 F6 C2 F6 C2
TRSIG 1 TSER2 TSIG2 TSER3 TSIG3
F4 32 F4 C32
F7 C32 F7 C32 F8 C32 F8 C32
F2 C1 F2 C1
F3 C1 F3 C1 F4 C1 F4 C1
F4 C1 F4 C1
F7 C1 F7 C1 F8 C1 F8 C1
F2 C2 F2 C2
F3 C2 F3 C2 F4 C2 F4 C2
F4 C2 F4 C2
F7 C2 F7 C2 F8 C2 F8 C2
BIT LEVEL DETAIL (4.096MHz bus configurtation) TSYSCLK TSYNC
4 FRAMER2, CHANNEL 32 FRAMER 1, CHANNEL 1
LSB MSB
FRAMER2, CHANNEL 1
LSB
TSER TSIG
A B C
LSB MSB
FRAMER2, CHANNEL 32
D
FRAMER 1, CHANNEL 1
A B C D
FRAMER2, CHANNEL 1
A B C D
Note 1: 4.096MHz bus configuration. Note 2: 8.192MHz bus configuration. Note 3: 16.384MHz bus configuration. Note 4: TSYNC is in input mode.
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Figure 34-23. Transmit IBO Frame Interleave Mode Timing
FRAMER #1, CHANNELS 1 through 32 TSSYNC TSER
1 F2 F2
F3 F3
F5 F6 F7
F1 F1
F4 F4
F8 F1
F2 F2
F2 F2 F3 F3
F5 F6 F7
F1 F1
F4 F4
F8 F1
F2 F2
F2 F2 F3 F3
F4 F5 F6 F7
TSIG1 TSER2 TSIG2 TSER3 TSIG3
F1 F1
F2 F3
F1 F1
F2 F3
F4 F4
F8
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
F2
F3
F4
F5
F6
F7
F8
BIT LEVEL DETAIL (4.096MHz bus configurtation) TSYSCLK TSYNC
4 FRAMER2, CHANNEL 32 FRAMER 1, CHANNEL 1
LSB MSB
FRAMER1, CHANNEL 2
LSB
TSER TSIG
A B C
LSB MSB
FRAMER2, CHANNEL 32
D
FRAMER 1, CHANNEL 1
A B C D
FRAMER1, CHANNEL 2
A B C D
Note 1: 4.096MHz bus configuration. Note 2: 8.192MHz bus configuration. Note 3: 16.384MHz bus configuration. Note 4: TSYNC is in input mode.
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35.
OPERATING PARAMETERS
-1.0V to +6.0V 0C to +70C -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS2156L Operating Temperature Range for DS2156LN Storage Temperature Range Soldering Temperature
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
THERMAL CHARACTERISTICS
PARAMETER Ambient Temperature Junction Temperature Theta-JA (qJA) in Still Air for 100-Pin LQFP SYMBOL CONDITIONS (Note 1) MIN -40C TYP MAX +85C +125C (Note 2) +32C/W UNITS
THETA-JA (qJA) vs. AIRFLOW
FORCED AIR (meters per second) 0 1 2.5 THETA-JA (qJA) 100-PIN LQFP +32C/W +27C/W +24C/W
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0C to +70C for DS2156L; TA = -40C to +85C for DS2156LN.)
PARAMETER Logic 1 Logic 0 Supply
SYMBOL VIH VIL VDD
CONDITIONS
MIN 2.0 -0.3 3.135
TYP
MAX 5.5 +0.8 3.465
UNITS V V V
(Note 3)
3.3
CAPACITANCE
(TA = +25C)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
CONDITIONS
MIN
TYP 5 7
MAX
UNITS pF pF
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DC CHARACTERISTICS
(VDD = 3.3V 5%, TA = 0C to +70C for DS2156L; VDD = 3.3V 5%, TA = -40C to +85C for DS2156LN.)
PARAMETER Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDD IIL ILO IOH IOL CONDITIONS (Note 4) (Note 5) (Note 6) MIN -1.0 -1.0 +4.0 TYP 75 +1.0 1.0 MAX UNITS mA mA mA mA mA
Note 1: The package is mounted on a four-layer JEDEC standard test board. Note 2: Theta-JA (qJA) is the junction to ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board. Note 3: Applies to RVDD, TVDD, and DVDD. Note 4: TCLK = TCLKI = RCLKI = TSYSCLK = RSYSCLK = MCLK = 1.544MHz; outputs open-circuited. Note 5: 0.0V < VIN < VDD Note 6: Applied to INT when three-stated.
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36.
AC TIMING PARAMETERS AND DIAGRAMS
Capacitive test loads are 40pF for bus signals, 20pF for all others.
36.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS: MULTIPLEXED PARALLEL PORT (MUX = 1)
(Figure 36-1, Figure 36-2, and Figure 36-3) (VDD = 3.3V 5%, TA = 0C to +70C for DS2156L; VDD = 3.3V 5%, TA = -40C to +85C for DS2156LN.)
PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/W Hold Time R/W Setup Time Before DS High CS Setup Time Before DS, WR, or RD Active CS Hold Time Read Data Hold Time Write Data Hold Time Muxed Address Valid to AS or ALE Fall Muxed Address Hold Time Delay Time DS, WR, or RD to AS or ALE Rise Pulse Width AS or ALE High Delay Time, AS or ALE to DS, WR or RD Output Data Delay Time from DS or RD Data Setup Time
SYMBOL tCYC PWEL PWEH tR , t F tRWH tRWS tCS tCH tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW
CONDITIONS
MIN 200 100 100
TYP
MAX
UNITS ns ns ns
20 10 50 20 0 10 0 15 10 20 30 10 20 50 80 50
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Figure 36-1. Intel Bus Read Timing (BTS = 0/MUX = 1)
t CYC ALE WR RD CS AD0-AD7 t ASL t AHL t DDR t DHR t ASD PW t ASD PWEL t ASED t CS
PWEH t CH
Figure 36-2. Intel Bus Write Timing (BTS = 0/MUX = 1)
t CYC ALE RD WR CS AD0-AD7 t ASL t AHL t DSW t DHW t ASD t ASD PWEL PW t ASED t CS
PWEH t CH
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Figure 36-3. Motorola Bus Timing (BTS = 1/MUX = 1)
PWASH AS t ASD DS PWEL t RWS R/W AD0-AD7 (read) t ASL t AHL
CS
t ASED t CYC
PWEH
t RWH t DDR t CH t DSW t DHW
t DHR
t CS
AD0-AD7 (write)
t ASL t AHL
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36.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS: NONMULTIPLEXED PARALLEL PORT (MUX = 0)
(Figure 36-4, Figure 36-5, Figure 36-6, and Figure 36-7) (VDD = 3.3V 5%, TA = 0C to +70C for DS2156L; VDD = 3.3V 5%, TA = -40C to +85C; for DS2156LN.)
PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR, or DS Active Delay Time from Either RD or DS Active to Data Valid Hold Time from Either RD, WR, or DS Inactive to CS Inactive Hold Time from CS Inactive to Data Bus Three-State Wait Time from Either WR or DS Active to Latch Data Data Setup Time to Either WR or DS Inactive Data Hold Time from Either WR or DS Inactive Address Hold from Either WR or DS Inactive
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9
CONDITIONS
MIN 0 0
TYP
MAX
UNITS ns ns
75 0 5 75 10 10 10 20
ns ns ns ns ns ns ns
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Figure 36-4. Intel Bus Read Timing (BTS = 0/MUX = 0)
A0 to A7 D0 to D7 WR CS
0ns (min)
ADDRESS VALID
DATA VALID 5ns (min) / 20ns (max)
t5
t1
0ns (min)
t2
t3
75ns (max)
t4
0ns (min)
RD
Figure 36-5. Intel Bus Write Timing (BTS = 0/MUX = 0)
A0 to A7 D0 to D7
ADDRESS VALID
t7
t8
10ns (min)
RD CS
10ns (min)
t1
0ns (min)
0ns (min)
t2
t6
75ns (min)
t4
0ns (min)
WR
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Figure 36-6. Motorola Bus Read Timing (BTS = 1/MUX = 0)
A0 to A7 D0 to D7 R/W CS
0ns (min)
ADDRESS VALID
DATA VALID 5ns (min) / 20ns (max)
t5
t1
0ns (min)
t2
t3
75ns (max)
t4
0ns (min)
DS
Figure 36-7. Motorola Bus Write Timing (BTS = 1/MUX = 0)
A0 to A7 D0 to D7
ADDRESS VALID
10ns (min)
R/W CS
t7 t8 t1
0ns (min)
10ns (min)
0ns (min)
t2
t6
75ns (min)
t4
0ns (min)
DS
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36.3 Receive-Side AC Characteristics AC CHARACTERISTICS: RECEIVE SIDE
(Figure 36-8, Figure 36-9, and Figure 36-10) (VDD = 3.3V 5%, TA = 0C to +70C for DS2156L; VDD = 3.3V 5%, TA = -40C to +85C for DS2156LN.)
PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse Width
SYMBOL tLP tLH tLL tLH tLL tCP tCH tCL
CONDITIONS
MIN
TYP 488 (E1) 648 (T1) 0.5 tLP 0.5 tLP 0.5 tLP 0.5 tLP 488 (E1) 648 (T1) 0.5 tCP 0.5 tCP 648 488 244 122
MAX
UNITS ns ns ns ns ns
(Note 1) (Note 1) (Note 2) (Note 2)
200 200 150 150
20 20 (Note 3) (Note 4)
ns ns
RSYSCLK Period
tSP
(Note 5) (Note 6) (Note 7)
RSYSCLK Pulse Width RSYNC Setup to RSYSCLK Falling RSYNC Pulse Width RPOSI/RNEGI Setup to RCLKI Falling RPOSI/RNEGI Hold From RCLKI Falling RSYSCLK, RCLKI Rise and Fall Times Delay RCLKO to RPOSO, RNEGO Valid Delay RCLK to RSER, RDATA, RSIG, RLINK Valid Delay RCLK to RCHCLK, RSYNC, RCHBLK, RFSYNC, RLCLK Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC
Note 1: Jitter attenuator enabled in the receive path.
tSH tSL tSU tPW tSU tHD tR, tF tDD tD1 tD2 tD3 tD4
20 20 20 50 20 20
61 0.5 tSP 0.5 tSP
ns ns ns ns ns ns 22 50 50 50 22 22 ns ns ns ns ns ns
Note 2: Jitter attenuator disabled or enabled in the transmit path. Note 3: RSYSCLK = 1.544MHz Note 4: RSYSCLK = 2.048MHz Note 5: RSYSCLK = 4.096MHz Note 6: RSYSCLK = 8.192MHz Note 7: RSYSCLK = 16.384MHz
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Figure 36-8. Receive-Side Timing
RCLK t D1 RSER / RDATA / RSIG RSYNC 1 RFSYNC / RMSYNC
t D2
1ST FRAME BIT
t D2 t D2
RCHCLK t D2 RCHBLK t D2 t D1 RLINK (T1MODE) 4 RLINK (E1 MODE)
Sa4 to Sa8 Bit Position
RLCLK 2
Note 1: RSYNC is in the output mode. Note 2: Shown is RLINK/RLCLK in the ESF framing mode. Note 3: No relationship between RCHCLK and RCHBLK and other signals is implied. Note 4: RLCLK only pulses high during Sa bit locations as defined in the E1RCR2 register.
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Figure 36-9. Receive-Side Timing, Elastic Store Enabled
tR tF t SL t SH t SP
RSYSCLK
t D3
RSER / RSIG
t D4
SEE NOTE 3
RCHCLK
t D4
RCHBLK
t D4
RMSYNC RSYNC 1 2
t D4 t HD t SU
RSYNC
Note 1: RSYNC is in the output mode. Note 2: RSYNC is in the input mode. Note 3: F-bit when MSTRREG.1 = 0, MSB of TS0 when MSTREG.1 = 1.
Figure 36-10. Receive Line Interface Timing
t LL RCLKO t DD RPOSO, RNEGO t LH
t LP
tR RCLKI
tF t SU
t CL
t CH
t CP
RPOSI, RNEGI t HD
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36.4 Transmit AC Characteristics AC CHARACTERISTICS: TRANSMIT SIDE
(Figure 36-11, Figure 36-12, and Figure 36-13) (VDD = 3.3V 5%, TA = -40C to +85C for DS2156L; VDD = 3.3V 5%, TA = 0C to +70C for DS2156LN)
PARAMETER TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width
SYMBOL tCP tCH tCL tLP tLH tLL
CONDITIONS
MIN
20 20
20 20 (Note 8) (Note 9) (Note 10) (Note 11) (Note 12) 20 20 20 50 20 20 20
TSYSCLK Period
tSP
TSYSCLK Pulse Width TSYNC or TSSYNC Setup to TCLK or TSYSCLK Falling TSYNC or TSSYNC Pulse Width TSER, TSIG, TDATA, TLINK, TPOSI, TNEGI Setup to TCLK, TSYSCLK, TCLKI Falling TSER, TSIG, TDATA, TLINK Hold from TCLK or TSYSCLK Falling TPOSI, TNEGI Hold from TCLKI Falling TCLK, TCLKI or TSYSCLK Rise and Fall Times Delay TCLKO to TPOSO, TNEGO Valid Delay TCLK to TESO, UT-UTDO Valid Delay TCLK to TCHBLK, TCHCLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, TCHBLK
Note 8: TSYSCLK = 1.544MHz Note 9: TSYSCLK = 2.048MHz Note 10: TSYSCLK = 4.096MHz Note 11: TSYSCLK = 8.192MHz Note 12: TSYSCLK = 16.384MHz
tSP tSU tPW tSU tHD tHD t R, t F tDD tD1 tD2 tD3
TYP (E1) 488 (E1) 648 (T1) 0.5 tCP 0.5 tCP 488 (E1) 648 (T1) 0.5 tLP 0.5 tLP 648 448 244 122 61 0.5 tSP 0.5 tSP
MAX
UNITS ns ns ns ns
ns
ns ns ns ns ns ns 25 50 50 50 22 ns ns ns ns ns
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Figure 36-11. Transmit-Side Timing
t CP tR TCLK t D1 TESO TSER / TSIG / TDATA t D2 TCHCLK TCHBLK t D2 TSYNC1 t SU TSYNC2 5 TLCLK t D2 t HD TLINK t SU t HD t D2 t SU t HD tF t CL t CH
Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Note 4: TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled. Note 5: In E1 mode, TLINK is only sampled during Sa bit locations as defined in E1TCR2; no relationship between TLCLK/TLINK and TSYNC is implied.
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Figure 36-12. Transmit-Side Timing, Elastic Store Enabled
t SP tR TSYSCLK t SU TSER t D3 TCHCLK t D3 TCHBLK t SU TSSYNC t HD t HD tF t SL t SH
Note 1: TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. Note 2: TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled.
Figure 36-13. Transmit Line Interface Timing
TCLKO
TPOSO, TNEGO t DD tR TCLKI t SU TPOSI, TNEGI t HD tF t LL t LP t LH
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36.5 UTOPIA Transmit AC Characteristics
PARAMETER Setup Time UT-ENB, UT-SOC, UT-ADDRx, UT-DATAx to UT-CLK Hold Time UT-ENB, UT-SOC, UT-ADDRx, UT-DATAx from UT-CLK Output Delay UT-CLAV, UT-2CLAV from UT-CLK UT-CLAV High-Z from UT-CLK SYMBOL tT5 tT6 td CONDITIONS MIN 10 1 20 25 TYP MAX UNITS ns ns ns ns
36.6 UTOPIA Receive AC Characteristics
PARAMETER Setup Time UR-ENB, UR-ADDRx to URCLK Hold Time UR-ENB, UR-ADDRx from URCLK Output Delay UR-CLAV, UR-DATAx, URSOC from UR-CLK UR-CLAV, UR-DATA, UR-SOC High-Z from UR-CLK SYMBOL tT5 tT6 td CONDITIONS MIN 10 1 20 25 TYP MAX UNITS ns ns ns ns
Figure 36-14. UTOPIA Interface Setup and Hold Times
CLOCK
SIGNAL tT5
INPUT SETUP TO CLOCK
tT6
INPUT HOLD FROM CLOCK
Figure 36-15. UTOPIA Interface Delay Times
CLOCK SIGNAL
td and tz
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37.
MECHANICAL DESCRIPTION
37.1 LQFP (L) Package
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